Abstract: Systems and methods for automated integration and stress testing of hardware and software services in a management controller using a containerized toolbox. The method utilizes a containerized toolbox module, which includes multiple testing tools for a web-based protocol, such as a Representational State Transfer (REST) protocol, and an Intelligent Platform Management Interface (IPMI) protocol. A management controller to be tested by the containerized toolbox module provides multiple services accessible under the web-based protocol and the IPMI protocol. In operation, the containerized toolbox module is provided at the management controller, and receives a testing command to perform a plurality of tests to the services of the management controller. Based on the testing command, the containerized toolbox module performs the tests to the services of the management controller using the testing tools of the containerized toolbox module.

Abstract: Systems and methods for automated integration and stress testing of hardware and software services in a management controller using a containerized toolbox. The method utilizes a containerized toolbox module, which includes multiple testing tools for a web-based protocol, such as a Representational State Transfer (REST) protocol, and an Intelligent Platform Management Interface (IPMI) protocol. A management controller to be tested by the containerized toolbox module provides multiple services accessible under the web-based protocol and the IPMI protocol. In operation, the containerized toolbox module is provided at the management controller, and receives a testing command to perform a plurality of tests to the services of the management controller. Based on the testing command, the containerized toolbox module performs the tests to the services of the management controller using the testing tools of the containerized toolbox module.

Abstract: A method is disclosed for localizing product yield variability to a process module. The method includes obtaining fail rate and critical area data for each process module layer in a number of test chips. A variance in a defect density (DD) probability density function (PDF) is determined based on the obtained fail rate and critical area data for each process module layer. A percent contribution from each process module layer to the variance in DD PDF is determined. Based on the determined percent contribution to the variance in DD PDF from each process module layer, one or more process module layers are identified as contributing to the determined variance in the DD PDF. Additionally, a method is provided to assess the impact on product yield due to reduction in the yield variability associated with a particular process module layer.

Abstract: Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.

Abstract: A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation.

Abstract: Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.

Abstract: A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.

Abstract: A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.