Patents by Inventor Surendranath Nagesh

Surendranath Nagesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Increasing the SNR of successive approximation type ADCs without compromising throughput performance substantially
    Patent number: 6894627
    Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 17, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Janakiraman, Kiran Manohar Godbole, Surendranath Nagesh
  • INCREASING THE SNR OF SUCCESSIVE APPROXIMATION TYPE ADCS WITHOUT COMPROMISING THROUGHPUT PERFORMANCE SUBSTANTIALLY
    Publication number: 20050057387
    Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 17, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Seetharaman Janakiraman, Kiran Godbole, Surendranath Nagesh