Patents by Inventor Suresh Balasubramanian
Suresh Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9335784Abstract: In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal.Type: GrantFiled: August 30, 2013Date of Patent: May 10, 2016Assignee: Cavium, Inc.Inventor: Suresh Balasubramanian
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Patent number: 9306584Abstract: A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.Type: GrantFiled: March 5, 2015Date of Patent: April 5, 2016Assignee: Cavium, Inc.Inventors: David Lin, Suresh Balasubramanian
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Patent number: 9264023Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.Type: GrantFiled: March 7, 2014Date of Patent: February 16, 2016Assignee: Cavium, Inc.Inventor: Suresh Balasubramanian
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Patent number: 9143140Abstract: A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.Type: GrantFiled: February 10, 2012Date of Patent: September 22, 2015Assignee: Cavium, Inc.Inventors: David Lin, Suresh Balasubramanian
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Patent number: 9130549Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.Type: GrantFiled: March 18, 2014Date of Patent: September 8, 2015Assignee: Cavium, Inc.Inventors: Suresh Balasubramanian, Nitin Mohan, Manan Salvi
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Publication number: 20150188528Abstract: A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte.Type: ApplicationFiled: March 5, 2015Publication date: July 2, 2015Inventors: David Lin, Suresh Balasubramanian
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Publication number: 20150067383Abstract: In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Cavium, Inc.Inventor: Suresh Balasubramanian
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Publication number: 20150061740Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.Type: ApplicationFiled: March 7, 2014Publication date: March 5, 2015Applicant: Cavium, Inc.Inventor: Suresh Balasubramanian
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Publication number: 20150061741Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.Type: ApplicationFiled: March 18, 2014Publication date: March 5, 2015Applicant: CAVIUM, INC.Inventors: Suresh Balasubramanian, Nitin Mohan, Manan Salvi
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Publication number: 20150061743Abstract: In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Cavium, Inc.Inventor: Suresh Balasubramanian
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Patent number: 8963601Abstract: In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value.Type: GrantFiled: August 30, 2013Date of Patent: February 24, 2015Assignee: Cavium, Inc.Inventor: Suresh Balasubramanian
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Patent number: 8513994Abstract: A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.Type: GrantFiled: February 9, 2012Date of Patent: August 20, 2013Assignee: Cavium, Inc.Inventor: Suresh Balasubramanian
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Patent number: 8381075Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.Type: GrantFiled: December 2, 2010Date of Patent: February 19, 2013Assignee: Texas Instruments IncorporatedInventors: David J. Toops, Sudhir K. Madan, Suresh Balasubramanian
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Publication number: 20120206181Abstract: A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.Type: ApplicationFiled: February 10, 2012Publication date: August 16, 2012Applicant: Cavium, Inc.Inventors: David Lin, Suresh Balasubramanian
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Publication number: 20120206178Abstract: A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.Type: ApplicationFiled: February 9, 2012Publication date: August 16, 2012Applicant: Cavium, Inc.Inventor: Suresh Balasubramanian
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Publication number: 20110231736Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.Type: ApplicationFiled: December 2, 2010Publication date: September 22, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: David J. Toops, Sudhir K. Madan, Suresh Balasubramanian
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Patent number: 7684274Abstract: In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC.Type: GrantFiled: December 10, 2007Date of Patent: March 23, 2010Assignee: Texas Instruments IncorporatedInventors: Santhana Rengarajan, Suresh Balasubramanian
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Patent number: 7568118Abstract: In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2005Date of Patent: July 28, 2009Assignee: Intel CorporationInventors: Warren R. Anderson, Maurice B. Steinman, Richard M. Watson, Horst W. Wagner, Christopher C. Gianos, Suresh Balasubramanian, Tim Frodsham
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Publication number: 20090147605Abstract: In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Inventors: Krishnan S. Rengarajan, Suresh Balasubramanian
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Patent number: 7349285Abstract: A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).Type: GrantFiled: February 2, 2005Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventors: Suresh Balasubramanian, Lakshmikantha V Holla, Bryan D Sheffield