Patents by Inventor Suresh Chemudupati
Suresh Chemudupati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220413591Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Pritesh P. SHAH, Suresh CHEMUDUPATI, Alexander GENDLER, David HUNT, Christopher M. MACNAMARA, Ofer NATHAN, Adwait PURANDARE, Ankush VARMA
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Publication number: 20220100247Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
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Patent number: 10496298Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.Type: GrantFiled: December 28, 2017Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Phani Kumar Kandula, Bharat S. Pillilli, Suresh Chemudupati, Yi-Feng Liu
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Publication number: 20190205042Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: Phani Kumar Kandula, Bharat S. Pillilli, Suresh Chemudupati, Yi-Feng Liu
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Patent number: 7506080Abstract: A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.Type: GrantFiled: September 16, 2005Date of Patent: March 17, 2009Assignee: Inter CorporationInventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, William Halleck
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Patent number: 7480832Abstract: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.Type: GrantFiled: June 24, 2005Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: Suresh Chemudupati, Victor T. Lau, Bruno DiPlacido, Eric J. DeHaemer
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Patent number: 7415549Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.Type: GrantFiled: September 27, 2005Date of Patent: August 19, 2008Assignee: Intel CorporationInventors: Kiran Vemula, Victor Lau, Pak-lung Seto, Nai-Chih Chang, William Halleck, Suresh Chemudupati, Ankit Parikh, Gary Y. Tsao
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Publication number: 20070073921Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.Type: ApplicationFiled: September 27, 2005Publication date: March 29, 2007Inventors: Kiran Vemula, Victor Lau, Pak-lung Seto, Nai-Chih Chang, William Halleck, Suresh Chemudupati
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Publication number: 20070073955Abstract: A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.Type: ApplicationFiled: September 29, 2005Publication date: March 29, 2007Inventors: Joseph Murray, Sailesh Bissessur, Shailendra Jha, Victor Lau, Bruno DiPlacido, Nai-Chih Chang, Suresh Chemudupati
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Publication number: 20070067504Abstract: A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.Type: ApplicationFiled: September 16, 2005Publication date: March 22, 2007Inventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, William Halleck
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Publication number: 20070011548Abstract: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.Type: ApplicationFiled: June 24, 2005Publication date: January 11, 2007Inventors: Suresh Chemudupati, Victor Lau, Bruno DiPlacido, Eric DeHaemer
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Publication number: 20070011333Abstract: Disclosed is an initiator port that implements a transport layer retry (TLR) mechanism. The initiator port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.Type: ApplicationFiled: June 30, 2005Publication date: January 11, 2007Inventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, Kiran Vemula, William Halleck, Ankit Parikh
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Publication number: 20070002827Abstract: Disclosed is a target port that implements a transport layer retry (TLR) mechanism. The target port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, Kiran Vemula, William Halleck, Ankit Parikh
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Publication number: 20030188056Abstract: A packet reformatter is disclosed that may store packet information received in one format and reformat the received packet information into a different format.Type: ApplicationFiled: March 27, 2002Publication date: October 2, 2003Inventor: Suresh Chemudupati