Patents by Inventor Suresh Chittor

Suresh Chittor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions
    Patent number: 6061764
    Abstract: Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: May 9, 2000
    Assignee: Intel Corporation
    Inventors: Suresh Chittor, Chih-Cheh Chen, Sin Sim Tan, Jonathan Nick Spitz
  • Method and an apparatus for minimizing perturbation while monitoring parallel applications
    Patent number: 6021457
    Abstract: A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes within the system to a very accurate global time clock such that all the nodes running the application stop and restart running the application at the same time. Within the time period bounded by the stop and restart time, all the performance monitoring data is transferred from performance monitoring data buffers to a secondary memory.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: David W. Archer, Don Breazeal, Suresh Chittor, Richard J. Greco, Wayne D. Smith, Jim Sutton
  • Bus protocol for atomic transactions
    Patent number: 5987552
    Abstract: A method for processing an atomic transaction in a multi-bus system that includes a local bus and a remote bus. According to the method, a first transaction in an atomic sequence is received from the local bus. The first transaction is terminated on the local bus. The first transaction is performed on the remote bus. A response to the first transaction is received and the response is placed on the local bus.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: November 16, 1999
    Assignee: Intel Corporation
    Inventors: Suresh Chittor, Suvansh Kapur, Lily Looi