Patents by Inventor Suresh Kadakia

Suresh Kadakia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR ENCRYPTION APPLICATIONS
    Publication number: 20080000988
    Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 3, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta Farooq, Benjamin Fasano, Jason Frankel, Harvey Hamel, Suresh Kadakia, David Long, Frank Pompeo, Sudipta Ray
  • METHOD AND STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR ENCRYPTION APPLICATIONS
    Publication number: 20060231633
    Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
    Type: Application
    Filed: April 14, 2005
    Publication date: October 19, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta Farooq, Benjamin Fasano, Jason Frankel, Harvey Hamel, Suresh Kadakia, David Long, Frank Pompeo, Sudipta Ray
  • Process for the manufacture of multilayer ceramic substrates
    Patent number: 6676784
    Abstract: A process for the manufacture of a multilayer ceramic substrate includes fabricating the multilayer ceramic substrate from a monolith fabricated from universal layers and a monolith fabricated from custom layers. The universal layer monolith and the custom layer monolith are then joined to form the complete structure of the MLC substrate.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: January 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Christopher D. Setzer, Harsaran S. Bahatia, Raymond M. Bryant, Michael S. Cranmer, Suresh Kadakia, Richard O. Seeger, Satyapal Singh Bhatia
  • SUBSTRATE DESIGN OF A CHIP USING A GENERIC SUBSTRATE DESIGN
    Publication number: 20030047352
    Abstract: A method of substrate design of an multilayer ceramic module that uses menu die of the same size is provided. One of these menu die provides a “generic” substrate design having internal wiring with greatest number of input/output (I/O) signal leads of all the dice available. Middle (redistribution) layers include electrical interconnections for both power and the I/O signal lead wires between the dice interface terminals and a bottom surface metallurgy (BSM) layer that has electrical connector pads by use of a customization layer.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Applicant: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Raymond M. Bryant, Suresh Kadakia, David C. Long, Paul R. Walling
  • Substrate design of a chip using a generic substrate design
    Patent number: 6528735
    Abstract: A method of substrate design of a multilayer ceramic module that uses menu die of the same size. One of these menu die provides a “generic” substrate design having internal wiring with the greatest number of input/output (I/O) signal leads of all the dies available. Middle (redistribution) layers include electrical interconnections for both power and the I/O signal lead wires between the die interface terminals and a bottom surface metallurgy (BSM) layer that has electrical connector pads by use of a customization layer.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Raymond M. Bryant, Suresh Kadakia, David C. Long, Paul R. Walling
  • Process for the manufacture of multilayer ceramic substrates
    Publication number: 20030015277
    Abstract: A process for the manufacture of a multilayer ceramic substrate includes fabricating the multilayer ceramic substrate from a monolith fabricated from universal layers and a monolith fabricated from custom layers. The universal layer monolith and the custom layer monolith are then joined to form the complete structure of the MLC substrate.
    Type: Application
    Filed: July 17, 2001
    Publication date: January 23, 2003
    Applicant: International Business Machines Corporation
    Inventors: Christopher D. Setzer, Harsaran S. Bahatia, Raymond M. Bryant, Michael S. Cranmer, Suresh Kadakia, Richard O. Seeger, Satyapal Singh Bhatia