Abstract: A high speed bus structure for a multi-port bridge for controlling the flow of data packets through the multi-port bridge by using a limited number of bus commands. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a memory pointer buffer. A data packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to determine which is the appropriate destination port for the packet. The destination ports are notified of their status as destination ports by raising a signal line of the communication bus corresponding to each destination port, referred to as a “bit-map.” If the memory pointer buffer in the destination port is nearly full, the destination port generates a jam request. The source port receives the jam request and, in response, discards the incoming packet and sends a jam signal.

Abstract: A selection technique for filtering packets in a multi-port bridge for a local area network, thus, preventing a source port for a packet from becoming a destination port for the packet. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a memory pointer buffer. A packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to determine which one or ones of the plurality of ports are the appropriate destination ports for the packet. Each of the ports is assigned a respective one of the signal lines of the communication bus. A product of utilizing the look-up tables is referred to as a bit-map of the destination ports for the packet. The bit-map includes a logic level for each signal line assigned to a port wherein the logic level is indicative of whether the corresponding port is a destination port for the packet.

Abstract: A technique for prioritizing accesses to a communication bus by data-communication ports in a multi-port bridge for a local area network. The bridge includes a plurality of ports interconnected by the bus. The bus includes signal lines dedicated to communicating commands, signal lines dedicated to communicating data, and several signal lines having special purposes. For example, two signal lines, are preferably dedicated to initiating different types of access to the bus, each having a respective priority. The ports are of two types (e.g. 100 Mbps or 10 Mbps data rates), each having a respective priority. A bus controller monitors the type of access to the bus attempted and the type of ports attempting access and grants access to the bus according to an appropriate priority.

Abstract: An external pulse width measuring circuit for use in a microprocessor system counts and stores the number of clock signals occurring in either a positive or negative going pulse. Short pulses may be measured to a 1 micro-second accuracy and the circuitry is capable of measuring very long pulses by the use of a counting prescaler and the ability of the timer to continue counting the prescaled pulses after reaching its full normal capacity.