Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

Abstract: Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error amplifier, a driver circuit, and a short-circuit protection circuit. The pass element is coupled to a power supply and a load, and generates an output voltage in response to a drive signal. The voltage error amplifier generates an error voltage based on a difference of a reference voltage and the output voltage and the driver circuit generates the drive signal in response to the error voltage. The short-circuit protection circuit senses the drive signal and provides a high-resistance path to the driver circuit in a short-circuit event. In a short-circuit event, the high-resistance path clamps current in the driver circuit thereby clamping a voltage difference between the first and third terminals and thereby limiting a load current in the short-circuit event.

Abstract: Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error amplifier, a driver circuit, and a short-circuit protection circuit. The pass element is coupled to a power supply and a load, and generates an output voltage in response to a drive signal. The voltage error amplifier generates an error voltage based on a difference of a reference voltage and the output voltage and the driver circuit generates the drive signal in response to the error voltage. The short-circuit protection circuit senses the drive signal and provides a high-resistance path to the driver circuit in a short-circuit event. In a short-circuit event, the high-resistance path clamps current in the driver circuit thereby clamping a voltage difference between the first and third terminals and thereby limiting a load current in the short-circuit event.

Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

Abstract: The systems and methods of auto-configurable switching/linear regulation disclosed herein enable a device to operate in both DC-to-DC switching regulation and linear regulation applications. The systems and methods disclosed herein differentiate between switching and linear mode. If the application is for a linear regulator, there will only be a capacitor on the output. If the application is for switching mode regulation, there will be an inductor and a capacitor on the output. Then based on the determination, the mode is selected and the hardware is converted into switching regulator operation or linear regulator operation.

Abstract: The systems and methods of auto-configurable switching/linear regulation disclosed herein enable a device to operate in both DC-to-DC switching regulation and linear regulation applications. The systems and methods disclosed herein differentiate between switching and linear mode. If the application is for a linear regulator, there will only be a capacitor on the output. If the application is for switching mode regulation, there will be an inductor and a capacitor on the output. Then based on the determination, the mode is selected and the hardware is converted into switching regulator operation or linear regulator operation.