Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication transmitter may monitor a clear channel assessment (CCA) for a primary bandwidth associated with the transmitter. The wireless communication transmitter may determine whether an interferer is located within the primary bandwidth based at least in part on tracking packet drops, within the primary bandwidth, that are based at least in part on the CCA. The wireless communication transmitter may monitor one or more additional CCAs for one or more secondary bandwidths associated with the transmitter. The wireless communication transmitter may determine whether an interferer is located within at least one bandwidth, of the one or more secondary bandwidths, based at least in part on tracking packet transmissions, within the one or more secondary bandwidths, that are based at least in part on the one or more additional CCAs. Numerous other aspects are described.

Abstract: An example assembly comprises: a main housing; an electric motor disposed in the main housing and comprising a stator fixedly positioned in the main housing, and a rotor positioned within the stator; a hydraulic pump positioned in the main housing and at least partially within the rotor, wherein the hydraulic pump is configured to receive fluid from an inlet port and provide fluid flow to an outlet port, wherein the hydraulic pump comprises a pump shaft rotatably coupled to the rotor of the electric motor; a controller housing coupled to the main housing; and a motor controller comprising one or more circuit boards disposed within the controller housing and configured to generate electric current to drive the electric motor.

Abstract: An example assembly comprises: a main housing; an electric motor disposed in the main housing and comprising a stator fixedly positioned in the main housing, and a rotor positioned within the stator; a hydraulic pump positioned in the main housing and at least partially within the rotor, wherein the hydraulic pump is configured to receive fluid from an inlet port and provide fluid flow to an outlet port, wherein the hydraulic pump comprises a pump shaft rotatably coupled to the rotor of the electric motor; a controller housing coupled to the main housing; and a motor controller comprising one or more circuit boards disposed within the controller housing and configured to generate electric current to drive the electric motor.

Abstract: One embodiment is directed to an open radio access network to provide wireless coverage for a plurality of cells at a site and that comprises a virtualized headend comprising one or more base-station nodes and a plurality of unified remote units deployed at the site. Each of the unified remote units is able to support multiple functional splits, multiple wireless interface protocols, multiple generations of radio access technology, and multiple frequency bands. The unified remote units and functional split used to serve each cell can be changed (for example, on-the-fly as a part of an automatic or manual adaptation process that is a function of one or more monitored performance attributes of the open radio access network such as network bandwidth, network latency, processing load, or processing performance). The unified remote units can be implemented in a modular manner with a backplane to which different radio modules can be coupled.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.

Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.

Abstract: An interface circuit that is configured to receive a first read command from a memory controller to read first data stored in a first memory circuit and a second read command to read second data that is stored in a second memory circuit, and transmit the first data and the second data to the memory controller across a data bus without a delay on the data bus between the first data and the second data.

Abstract: Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.