Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard.

Abstract: A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.

Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.

Abstract: A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.

Abstract: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

Abstract: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Abstract: A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component.

Abstract: A memory apparatus includes multiple memory circuits and an interface circuit to present to a host system emulated memory circuits. The interface circuit includes a first component of a first type and a second component of a second type, the first component and the second component being operable to present a host-system interface to the host system and to present a memory-circuit interface to the plurality of memory circuits, in which there is a difference in at least one aspect between the host-system interface and the memory circuit interface. At least one of the first and second components is operable to identify one or more memory circuits that is not being accessed and to perform a power-saving operation on the one or more memory circuits identified as not being accessed, where the power-saving operation includes placing the memory circuits identified as not being accessed in a precharge power down mode.

Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Abstract: One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.

Abstract: A method includes: receiving first information in association with a first operation to be performed on at least one of multiple flash memory circuits; storing at least a portion of the first information; receiving second information in association with a second operation to be performed on at least one of the multiple flash memory circuits, in which the second operation is a read operation or a write operation; receiving data from the flash memory circuits based on at least the first information and storing the data in a buffer; and performing the second operation utilizing the stored portion of the first information in addition to the second information on the data in the buffer.

Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard.

Abstract: One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

Abstract: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Abstract: A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.

Abstract: One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

Abstract: An interface circuit that emulates a memory circuit having a first organization using a memory circuit having a second organization, wherein the second organization includes a number of banks, a number of rows, a number of columns, and a number of bits per column.

Abstract: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.