Patents by Inventor Suresh Venkumahanti
Suresh Venkumahanti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9384825Abstract: A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.Type: GrantFiled: September 26, 2014Date of Patent: July 5, 2016Assignee: QUALCOMM IncorporatedInventors: Jentsung Lin, Paul Bassett, Suresh Venkumahanti
-
Patent number: 9361109Abstract: A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter. The apparatus also includes a decode unit configured to receive the second instruction from the location and to decode the second instruction to generate a decoded second instruction without changing the program counter to point to the second instruction.Type: GrantFiled: May 24, 2010Date of Patent: June 7, 2016Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
-
Publication number: 20160093363Abstract: A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Jentsung LIN, Paul BASSETT, Suresh VENKUMAHANTI
-
Patent number: 8990543Abstract: In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.Type: GrantFiled: March 11, 2008Date of Patent: March 24, 2015Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Robert Allan Lester, Charles Joseph Tabony, Erich James Plondke, Mao Zeng, Suresh Venkumahanti, Ajay Anant Ingle
-
Patent number: 8725991Abstract: The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.Type: GrantFiled: September 12, 2007Date of Patent: May 13, 2014Assignee: QUALCOMM IncorporatedInventors: Lin Wang, Masud Kamal, Paul Bassett, Suresh Venkumahanti, Jian Shen
-
Patent number: 8533530Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.Type: GrantFiled: November 15, 2006Date of Patent: September 10, 2013Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, William C. Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen
-
Patent number: 8380966Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.Type: GrantFiled: November 15, 2006Date of Patent: February 19, 2013Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, William C. Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen
-
Patent number: 8370806Abstract: A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.Type: GrantFiled: November 15, 2006Date of Patent: February 5, 2013Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, William C. Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen
-
Patent number: 8341604Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution.Type: GrantFiled: November 15, 2006Date of Patent: December 25, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, William C. Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen
-
Patent number: 8145874Abstract: In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.Type: GrantFiled: February 26, 2008Date of Patent: March 27, 2012Assignee: QUALCOMM IncorporatedInventors: Suresh Venkumahanti, Lucian Codrescu, Lin Wang
-
Patent number: 8140823Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.Type: GrantFiled: December 3, 2007Date of Patent: March 20, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
-
Publication number: 20110289299Abstract: A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter. The apparatus also includes a decode unit configured to receive the second instruction from the location and to decode the second instruction to generate a decoded second instruction without changing the program counter to point to the second instruction.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Applicant: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
-
Patent number: 7941646Abstract: A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.Type: GrantFiled: December 31, 2007Date of Patent: May 10, 2011Assignee: Freescale Semicondoctor, Inc.Inventors: David C. Holloway, Michael D. Snyder, Suresh Venkumahanti
-
Patent number: 7827356Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.Type: GrantFiled: September 10, 2007Date of Patent: November 2, 2010Assignee: QUALCOMM IncorporatedInventors: Suresh Venkumahanti, Phillip Matthew Jones
-
Patent number: 7657791Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.Type: GrantFiled: November 15, 2006Date of Patent: February 2, 2010Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, William C. Anderson, Suresh Venkumahanti, Louis Achille Giannini, Manojkumar Pyla, Xufeng Chen
-
Publication number: 20090235051Abstract: In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Applicant: QUALCOMM INCORPORATEDInventors: Lucian Codrescu, Robert Allan Lester, Charles Joseph Tabony, Erich James Plondke, Mao Zeng, Suresh Venkumahanti, Ajay Anant Ingle
-
Publication number: 20090172361Abstract: A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: David C. Holloway, Michael D. Snyder, Suresh Venkumahanti
-
Publication number: 20090144519Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.Type: ApplicationFiled: December 3, 2007Publication date: June 4, 2009Applicant: QUALCOMM INCORPORATEDInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
-
Publication number: 20090070554Abstract: The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.Type: ApplicationFiled: September 12, 2007Publication date: March 12, 2009Applicant: QUALCOMM INCORPORATEDInventors: Lin Wang, Masud Kamal, Paul Bassett, Suresh Venkumahanti, Jian Shen
-
Publication number: 20090070531Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: QUALCOMM INCORPORATEDInventors: Suresh Venkumahanti, Phillip Matthew Jones