Abstract: Described is an improved storage architecture. In a particular aspect an improved storage architecture with increased throughput to Ethernet storage modules due to elimination of data path handling from a main control CPU is set forth. Other method and apparatus are described therein, including a scalable Ethernet storage module particularly suited for usage with the improved storage architecture described herein.

Abstract: Described is a redundant array of inexpensive disks (RAID) scheme that manages the wear of individual drives in a RAID set and significantly reduces the probability of more than two drives wearing out at the same time. In one aspect, describe is a method in which at least one of a first and second of the plurality of at least three low endurance flash based solid state devices perform a predetermined percentage of more writes as compared to at least a third of the plurality of at least three low endurance flash based solid state devices. In another aspect, a rebuild operation is performed using Galois Field Multiplication, with one of an integrated circuit and a field programmable gate array (FPGA) being used in preferred implementations.

Abstract: Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.

Abstract: Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

Abstract: Described is an improved storage architecture. In a particular aspect an improved storage architecture with increased throughput to Ethernet storage modules due to elimination of data path handling from a main control CPU is set forth. Other method and apparatus are described therein, including a scalable Ethernet storage module particularly suited for usage with the improved storage architecture described herein.

Abstract: One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

Abstract: One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

Abstract: Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

Abstract: One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

Abstract: Systems and techniques for processing and forwarding packets are described. Some embodiments provide a system (e.g., a switch) which determines an internal virtual network identifier and/or an internal policy identifier for a packet based on a port on which the packet was received and/or one or more fields in the packet. The system can then process and forward the packet based on the internal virtual network identifier and/or internal policy identifier. In some embodiments, the system encapsulates the packet in a TRILL (Transparent Interconnection of Lots of Links) packet by adding a TRILL header to the packet. In some embodiments, the scope of an internal virtual network identifier and/or an internal policy identifier may not extend beyond a switch or a module within a switch.

Abstract: A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

Abstract: A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

Abstract: The present invention provides a system and a method for filtering a plurality of frames sent between devices coupled to a fabric by Fiber Channel connections. Frames are reviewed against a set of individual frame filters. Each frame filter is associated with an action, and actions selected by filter matches are prioritized. Groups of devices are “zoned” together and frame filtering ensures that restrictions placed upon communications between devices within the same zone are enforced. Zone group filtering is also used to prevent devices not within the same zone from communicating. Zoning may also be used to create LUN-level zones, protocol zones, and access control zones. In addition, individual frame filters may be created that reference selected portions of frame header or frame payload fields.

Abstract: A system and method for performing an inverse discrete cosine transform (IDCT) based on DCT data is disclosed. The system is IEEE compliant and transforms one block (8×8) of pixels in 64 cycles. The IDCT processor receives the DCT input, produces the matrix (QXTQ)P, or XQP, in IDCT Stage 1 and stores the result in transpose RAM. IDCT Stage 2 performs the transpose of the result of IDCT Stage 1 and multiplies the result by P, completing the IDCT process and producing the IDCT output. The system performs the matrix function QXtQ, where X represents the DCT data and Q is a predetermined diagonal matrix. The resultant value is adjusted by discarding selected bits, and the system then postmultiplies this with the elements of a predetermined P matrix, and discards selected bits. The system performs a conversion and storing function and performs a sign change to obtain QXtQP. This completes first stage processing, which is then passed to transpose RAM.

Abstract: A system and method for performing motion compensation in an MPEG video decoder. The system comprises a horizontal half pixel compensation arrangement including multiple adders and multiplexers which perform horizontal half pixel compensation using an addition function, a division function, and a modulo function on pixel data. The system also includes a register bank which provides the ability to store an array of reference data when vertical half pixel compensation is required. The system also includes a verical half pixel compensation arrangement, which also includes multiple adders and multiplexers which perform vertical half pixel compensation using an addition function, a division function, and a modulo function on pixel data. Reference data and odd pixel data is transferred into and within the system in a predetermined arrangement. Reference and odd pel data may comprise either luma or chroma data.

Abstract: A system and method for low delay mode operation video decoding embodied in a prefetch buffer and an mbcore including an mbcore pipeline. The mbcore is adapted to check a status of the prefetch buffer at predetermined times and to implement a low delay mode to delay the mbcore pipeline when a data level of the prefetch buffer goes below a threshold at the predetermined times. The mbcore is adapted to ensure that there is a sufficient quantity of data in the prefetch buffer for a particular operation and, in a preferred embodiment, is adapted to check the status of the prefetch buffer at a start of a slice, at a beginning of dct decoding of each coded block. The prefetch buffer and the mbcore operate asynchronously, with the mbcore being adapted to prevent a symbol from splitting between the prefetch buffer and the mbcore.

Abstract: A system and method for decoding an MPEG video bitstream comprising several macroblocks of data is disclosed. The system comprises a macroblock core (MBCORE) which processes video bitstream data and computes discrete cosine transform data corresponding to the processed video bitstream, and a parser which parses the video bitstream macroblocks into multiple data blocks used in subsequent stages of decoding. The system further includes a transformation/motion compensation core (TMCCORE) which is divided into multiple stages. The TMCCORE includes an IDCT first stage, an intermediate memory (transpose RAM), and an IDCT second stage. The IDCT first stage passes data to memory and the IDCT second stage receives data from memory. The IDCT first stage has the ability to operate on a first data block while the second stage simultaneously operates on a second data block. The TMCCORE receives the discrete cosine transform data from the MBCORE and calculates and reconstructs a frame therefrom using motion compensation.

Abstract: A system and method for decoding an MPEG video bitstream comprises, comprising a macroblock core (MBCORE) which processes video bitstream data and computes discrete cosine transform data and a parser which parses the video bitstream macroblocks into multiple data blocks used in subsequent stages of decoding. fixed length data words comprising variable length objects using a novel rotating register arrangement. A multistage transformation/motion compensation core (TMCCORE) uses intermediate memory. The IDCT first stage has the ability to operate on a first data block while the second stage simultaneously operates on a second data block. The TMCCORE receives the discrete cosine transform data from the MBCORE and calculates and reconstructs a frame therefrom using motion compensation. The MBCORE can operate on data from a first macroblock while the TMCCORE simultaneously operates on data from a second macroblock.

Abstract: A system and method for decoding fixed length data words comprising variable length objects is disclosed having the ability to decode a variable length DCT in every clock cycle. The system includes multiple floating point registers, preferably two, for holding the fixed length data words, and a tracking arrangement, including a summation block and a total used bits register, where the summation block sums bits used for each variable length object with the contents of the total bits used register to form the total number of used bits. The total used bits are fed back and summed within the total used bits register.The system also has a rotating shift register, which is a circular buffer, and a multiplexer arrangement which transfers variable length objects from the floating point registers to the rotating shift register. The tracking arrangement counts the bits used in transferring variable length objects to the rotating shift register.