Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A method for validating data in a hybrid cloud model that includes providing a validation layer in the brokerage module of the hybrid architecture. The validation layer is separate from an applications layer of the hybrid architecture. The method includes sending target object values to a centralized brokerage layer composite query generator (BLCQG) component of the validation layer from an application needing validation of target data time. The method continues with generating a composite validation rule set with the brokerage layer composite query generator (BLCQG) component based on the parameters of the target object values. The method further includes validating the target data item of the target object values with the composite validation rule in the validation rules validator (VRV) component; and sending the target data item that has been validated to the application.

Abstract: A method, a system and a computer program product for automated ASCII-based object-oriented database schema (OODBS) generation. A parser runs through text sentences of a textual document from a requirements gathering team that includes object-oriented application requirements, and identifies nouns corresponding to an object, and each noun's attributes. An Object-oriented dictionary based ASCII interpreter analyzes the ASCII of the captured requirements. For each identified noun, the system creates first key-value structures mapping each identified object to one or more associated attributes. There is further identified, from the created first key-value structures, any attributes that reference to an identified object, and for each of these identified objects, the system creates second key-value structures mapping, for each attribute identified as a reference, associating a corresponding key where the reference is found as an attribute.

Abstract: Relational database schema generation includes obtaining an input requirements specification for a relational database to be generated, interpreting text characters of the requirements specification as values of a predefined character encoding, parsing the interpreted text characters and identifying complete sentences of the requirements specification, identifying, using an input dictionary that specifies combinations of character values of the predefined character encoding, proper nouns in the identified complete sentences and common nouns in the identified complete sentences, and generating a relational database schema script for the relational database, the generating including indicating the identified proper nouns of the complete sentences as entities of the relational database and indicating the identified common nouns of the complete sentences as attributes of those entities.

Abstract: Disclosed embodiments provide techniques for load balancing of computer jobs in a distributed computer network. A health score is determined for each node of the pool of nodes, which can include native applications, virtual machines, and/or containers. A future resource availability score is determined for each node of the pool of nodes corresponding with a predetermined future time. A schedule eligibility score is computed for each node based on the health score and future resource availability score. A new job is assigned to the node with the optimal schedule eligibility score. In this way, rather than only considering the current workload conditions of the node, a future resource availability score is computed for each node, and this score is used as a factor in the assigning of jobs to the node. This provides an opportunity for improved resource utilization and improved overall system reliability.

Abstract: Systems and methods for dynamic incremental updating of online analytical processing (OLAP) data cubes are disclosed. In embodiments, a computer-implemented method, comprises: receiving real-time transactional event data including a plurality of data fields; identifying aggregate computing functions for each of a plurality of standard query language (SQL) queries of a target data cube to be updated, wherein the target data cube is in a multidimensional form for storing OLAP data in the form of numeric values organized in fields; incrementally calculating the aggregate computing functions based on a current aggregated value obtained from an updated aggregated field database, and a value of one of the plurality of data fields; repeating the incremental calculation for each of the plurality of SQL queries to obtain updated field data for the target data cube; and updating the updated aggregated field database with the updated field data.

Abstract: An approach is provided for delivering a configuration based workflow in an IT system. A set of parameters and pre-configured conditions associated with a command initiated for execution are determined. Validation action(s) that validate the command and are included in the configuration based workflow are determined. The validation action(s) are specified by respective interaction(s) with external system(s). Validation action(s) included in the configuration based workflow are performed by completing the interaction(s) with the external system(s) using the set of parameters. It is determined whether the validation action(s) are successfully completed. If the validation action(s) are successfully completed, the execution of the command is continued. If at least one of the validation action(s) is not successfully completed, the execution of the command is discontinued.

Abstract: An approach is provided for delivering a configuration based workflow in an IT system. A command initiated for execution is identified as being included in a list of commands. A set of parameters and pre-configured conditions associated with the identified command are determined. Validation action(s) that validate the command and are included in the configuration based workflow are determined. The validation action(s) are specified by respective interaction(s) with external system(s). Validation action(s) included in the configuration based workflow are performed by completing the interaction(s) with the external system(s) using the set of parameters. It is determined whether the validation action(s) are successfully completed. If the validation action(s) are successfully completed, the execution of the command is continued. If at least one of the validation action(s) is not successfully completed, the execution of the command is discontinued.

Abstract: An approach is provided for delivering a configuration based workflow in an IT system. A command initiated for execution is identified as being included in a list of commands. A set of parameters and pre-configured conditions associated with the identified command are determined. Validation action(s) that validate the command and are included in the configuration based workflow are determined. The validation action(s) are specified by respective interaction(s) with external system(s). Validation action(s) included in the configuration based workflow are performed by completing the interaction(s) with the external system(s) using the set of parameters. It is determined whether the validation action(s) are successfully completed. If the validation action(s) are successfully completed, the execution of the command is continued. If at least one of the validation action(s) is not successfully completed, the execution of the command is discontinued.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.

Abstract: An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.

Abstract: Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.

Abstract: Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.

Abstract: The present invention relates to the use of cannabinoid receptor modulators, particularly selective CB2 receptor agonists, for treating non-immediate type allergic diseases in mammals. The invention further relates to a pharmaceutical composition for non-immediate type allergic diseases.