Abstract: Methods and systems for selectively processing VLAN traffic from different networks while allowing flexible VLAN identifier assignment are disclosed. According to one aspect, a layer 2 switch includes a virtual switch identifier data structure that associates a VLAN identifier extracted from a layer 2 frame and a port identifier corresponding to a port on which a frame is received with a virtual switch identifier. The virtual switch identifier is used to select a per-virtual-switch data structure, such as a forwarding table. The per-virtual-switch data structure is used to control processing of the layer 2 frame on a per-virtual-switch basis. The per-virtual-switch data structure may also be updated separately from the data structures assigned to other virtual switches.

Abstract: Methods and systems for selectively processing VLAN traffic from different networks while allowing flexible VLAN identifier assignment are disclosed. According to one aspect, a layer 2 switch includes a virtual switch identifier data structure that associates a VLAN identifier extracted from a layer 2 frame and a port identifier corresponding to a port on which a frame is received with a virtual switch identifier. The virtual switch identifier is used to select a per-virtual-switch data structure, such as a forwarding table. The per-virtual-switch data structure is used to control processing of the layer 2 frame on a per-virtual-switch basis. The per-virtual-switch data structure may also be updated separately from the data structures assigned to other virtual switches.

Abstract: Methods and systems for selectively processing VLAN traffic from different networks while allowing flexible VLAN identifier assignment are disclosed. According to one aspect, a layer 2 switch includes a virtual switch identifier data structure that associates a VLAN identifier extracted from a layer 2 frame and a port identifier corresponding to a port on which a frame is received with a virtual switch identifier. The virtual switch identifier is used to select a per-virtual-switch data structure, such as a forwarding table. The per-virtual-switch data structure is used to control processing of the layer 2 frame on a per-virtual-switch basis. The per-virtual-switch data structure may also be updated separately from the data structures assigned to other virtual switches.

Abstract: Methods and systems for selectively processing VLAN traffic from different networks while allowing flexible VLAN identifier assignment are disclosed. According to one aspect, a layer 2 switch includes a virtual switch identifier data structure that associates a VLAN identifier extracted from a layer 2 frame and a port identifier corresponding to a port on which a frame is received with a virtual switch identifier. The virtual switch identifier is used to select a per-virtual-switch data structure, such as a forwarding table. The per-virtual-switch data structure is used to control processing of the layer 2 frame on a per-virtual-switch basis. The per-virtual-switch data structure may also be updated separately from the data structures assigned to other virtual switches.

Abstract: A connection pacer and method for performing connection pacing in a network of servers and clients using a first-in-first-out (“FIFO”) buffer.

Abstract: A debugging architecture includes a set of debug counters for counting one or more events based on a set of signals from a device being monitored. The architecture provides for observing the outputs of the debug counters during operation of the device. The outputs of the counters are provided to an output bus (e.g., a Debug Bus) via an output bus interface during operation of the device being monitored. A data gathering system can access the output bus in order to gather the data from the counters for analysis.

Abstract: A hardware implemented transactional memory system includes a mechanism to allow multiple processors to access the same memory system. A set of timestamps are stored that each correspond to a region of memory. A time stamp is updated when any memory in its associated region is updated. For each memory transaction, the time at which the transaction begins is recorded. Write operations that are part of a transaction are performed by writing the data to temporary memory. When a transaction is to be recorded, the hardware automatically commits the transaction by determining whether the timestamps associated with data read for the transaction are all prior to the start time for the transaction. In this manner, the software need not check the data for all other processes or otherwise manage collision of data with respect to different processes. The software need only identify which reads and writes are part of a transaction.

Abstract: A hardware implemented transactional memory system includes a mechanism to allow multiple processors to access the same memory system. A set of timestamps are stored that each correspond to a region of memory. A time stamp is updated when any memory in its associated region is updated. For each memory transaction, the time at which the transaction begins is recorded. Write operations that are part of a transaction are performed by writing the data to temporary memory. When a transaction is to be recorded, the hardware automatically commits the transaction by determining whether the timestamps associated with data read for the transaction are all prior to the start time for the transaction. In this manner, the software need not check the data for all other processes or otherwise manage collision of data with respect to different processes. The software need only identify which reads and writes are part of a transaction.

Abstract: Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software before and/or during processor instruction execution. The no-dispatch condition can be associated with a number of processing cycles and an instruction from a particular thread. As a result of generating the no-dispatch condition, processor instructions from other threads may be dispatched into the execution slot of an available execution pipeline. After a period of time, the instruction associated with the stall can be fetched and executed.

Abstract: An adaptive forward differencing apparatus, wherein, when rendering curves, calculated x, y values are increased or decreased in order to create values which correspond to the next pixel of the display CRT, such that curves of substantially one pixel increments are continuously and uniformly generated. The apparatus also provides circuitry for generating coordinates of display elements which approximate an ideal vector and to define curves, vectors or objects within maximum and minimum coordinates of the CRT display. The apparatus also provides efficient circuitry for computing the value of 1/w of the homogenous coordinate w.

Abstract: A pixel buffer separate from the frame buffer is provided to store selected pixel information, including XYZ values, sub-pixel coverage, and a color value for a graphic object. The frame buffer stores pixel information for each pixel on the screen, including sub-pixel coverage. During the rendering process, the pixel information for each graphic object is computed and stored in the frame buffer. However, as subsequent pixel information for the same XY pixel locations are computed, it may be impossible to combine the two separate sets of pixel information into a single set of pixel information while maintaining the pixel information required to combine the single set of pixel information with subsequent pixel information to be rendered to the same XY location. To maintain the pixel information needed, the first set of pixel information is stored in the frame buffer and the second set of pixel information is stored in the pixel buffer.

Abstract: The present invention provides unique methods and apparatus for shading curves, polygons and patches, implementing Phong, Gouraud and other shading techniques in the rendering of images on a cathode ray tube or other display device. The present invention also includes a unique method and apparatus for shading patches by rendering a series of adjacent curves such that no pixel gaps exist between each rendered curve.

Abstract: An asynchronous micro-machine/interface responsive to a central processing unit (CPU) in which the CPU and the micro-machine/interface are run on clocks which are asynchronous from one another is provided. The inventive asynchronous micro-machine/interface has data path elements for receiving an incoming instruction and for performing actions requested by the incoming instruction, as well as a means for synchronizing the incoming instruction to the clock of the micro-machine/interface and for performing actions within the data path elements prior to the execution of the incoming instruction and during transfer of control, by the micro-machine/interface, to the routine that is associated with the incoming instruction.

Abstract: An adaptive forward differencing apparatus wherein, when rendering curves, calculated x, y values are increased or decreased in order to create values which correspond to the next pixel of the display CRT, such that curves of substantially one pixel increments are continuously and uniformly generated. The apparatus of the present invention also provides circuitry for generating coordinates of display elements which approximate an ideal vector and to define curves, vectors or objects within maximum and minimum coordinates of the CRT display. The present invention also provides efficient circuitry for computing the value of 1/w of the homogenous coordinate w.