Patents by Inventor Susan E. Soggs

Susan E. Soggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Combined trench isolation and inlaid process for integrated circuit formation
    Patent number: 5963818
    Abstract: A method for forming an integrated circuit involves forming trench isolation regions (208a) and a damascene gate electrode region (214) simultaneous with one another via overlapping process steps. By performing this simultaneous formation of a trench region (208a) and a damascene gate electrode (214) using a common dielectric layer (208), MOS integrated circuits can be formed with reduced processing steps while simultaneously avoiding adverse polysilicon stringers which are present in prior art damacene-formed gate electrode. A single dielectric layer (208) is deposited in order to provide trench fill material for a trench region (208a) while simultaneously providing the material needed for form an opening (210) which is used to define the dimensions and material content of a gate electrode (214).
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: October 5, 1999
    Assignee: Motorola, Inc
    Inventors: Soolin Kao, Sergio A. Ajuria, Diann M. Dow, Susan E. Soggs