Patents by Inventor Susan Johns
Susan Johns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990665Abstract: An antenna system for space applications provides a membrane antenna with one or more flexible membranes. An antenna enclosure stores the membrane antenna during stowage. One or more first deployable support structures extend along a first axis from the antenna enclosure during deployment, at least a first point of the membrane antenna being operably anchored to a point on the first deployable support structures. Deployment mechanisms are operably anchored at a junction with the first deployable support structures. The deployment mechanisms extend one or more second deployable support structures along a second axis from the first deployable support structures during deployment. At least a second point of the membrane antenna is operably anchored to a point on the second deployable support structures. Extension of the first deployable support structures and second deployable support structures unfurls the membrane antenna along both axes to overlap the junction.Type: GrantFiled: August 3, 2022Date of Patent: May 21, 2024Assignee: M.M.A. Design, LLCInventors: Timothy John Ring, Susan Christine Tower
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Publication number: 20240151613Abstract: A method to extract a mycotoxin, or a plurality of mycotoxins, from a sample carrier into a solvent solution. The mycotoxin may have been an initially airborne mycotoxin initially captured by a filter that functions as the sample carrier. The method may generally include the steps of at least partially immersing or wetting the sample carrier within a solvent solution carried by a vessel; agitating the sample carrier within the solvent solution to extract at least some of the mycotoxin from the sample carrier; and removing the sample carrier from the vessel.Type: ApplicationFiled: March 11, 2022Publication date: May 9, 2024Inventors: Robert John Goldsworthy, Susan Goldsworthy
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Publication number: 20240090556Abstract: A method of forming a heat-treated liquid nutritional composition having a neutral pH and comprising a water-insoluble plant flavonoid comprises providing an aqueous liquid nutritional composition having a pH of from about 6 to about 7.5 and comprising protein, fat, carbohydrate, and water-insoluble plant flavonoid, homogenizing the liquid nutritional composition at a pressure of at least about 2000 psi, and heat treating the liquid nutritional composition. A heat-treated liquid nutritional composition having a pH of from about 6 to about 7.5 comprises a water-insoluble plant flavonoid, protein, fat and carbohydrate. At least about 75 wt % of the water-insoluble plant flavonoid remains suspended throughout the liquid nutritional composition after two months of storage at room temperature.Type: ApplicationFiled: November 29, 2021Publication date: March 21, 2024Inventors: Quang Son PHAM, Suzette L. PEREIRA, Paul JOHNS, Susan WANG, Megan TERP, Ricardo Rueda Cabrera
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Patent number: 11789609Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules. The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.Type: GrantFiled: September 1, 2022Date of Patent: October 17, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Raymond-Noel Nkoulou Kono, Nisha Susan John
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Publication number: 20230244784Abstract: A system for detecting access to a security sensitive component on an electronic device includes a PCB-mounted connector that provides read/write access to a security sensitive component on the PCB. The system further includes a connector cap that mates with at least a portion of the connector and that includes circuitry that facilitates current flow across at least a portion of the PCB-mounted connector when the connector cap is mated with the PCB-mounted connector, When removed from the PCB-mounted connector, the current flow is disrupted. The system further includes an intrusion detection controller that monitors a voltage at a sampling point adjacent to detect removal of the connector cap and to generate an intrusion logfile entry in response.Type: ApplicationFiled: February 1, 2022Publication date: August 3, 2023Inventors: Benito Joseph RODRIGUEZ, Nisha Susan JOHN
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Publication number: 20230004295Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules, The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.Type: ApplicationFiled: September 1, 2022Publication date: January 5, 2023Inventors: Raymond-Noel Nkoulou KONO, Nisha Susan JOHN
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Patent number: 11467729Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules. The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.Type: GrantFiled: June 29, 2020Date of Patent: October 11, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Raymond-Noel Nkoulou Kono, Nisha Susan John
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Publication number: 20210405874Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules. The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: Raymond-Noel Nkoulou KONO, Nisha Susan JOHN
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Patent number: 9761550Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: GrantFiled: April 13, 2016Date of Patent: September 12, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Robert Montgomery, Hugo Burke, Phillip Parsonage, Susan Johns, David Paul Jones
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Publication number: 20160233185Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: ApplicationFiled: April 13, 2016Publication date: August 11, 2016Inventors: Robert Montgomery, Hugo Burke, Phillip Parsonage, Susan Johns, David Paul Jones
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Patent number: 9318355Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: GrantFiled: July 17, 2014Date of Patent: April 19, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
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Publication number: 20140327057Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
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Patent number: 8791525Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: GrantFiled: February 25, 2008Date of Patent: July 29, 2014Assignee: International Rectifier CorporationInventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
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Patent number: 8143729Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.Type: GrantFiled: January 26, 2009Date of Patent: March 27, 2012Assignee: International Rectifier CorporationInventors: Mark Pavier, Danish Khatri, Daniel Cutler, Andrew Neil Sawle, Susan Johns, Martin Carroll, David Paul Jones
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Publication number: 20090218684Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.Type: ApplicationFiled: January 26, 2009Publication date: September 3, 2009Inventors: Mark Pavier, Danish Khatri, Daniel Cutler, Andrew Neil Sawle, Susan Johns, Martin Carroll, David Paul Jones
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Publication number: 20090212435Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
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Patent number: 6593172Abstract: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected.Type: GrantFiled: May 21, 2001Date of Patent: July 15, 2003Assignee: International Rectifier CorporationInventor: Susan Johns
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Publication number: 20020168801Abstract: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected.Type: ApplicationFiled: May 21, 2001Publication date: November 14, 2002Applicant: ESM LimitedInventor: Susan Johns