Patents by Inventor Susan Morton
Susan Morton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881851Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.Type: GrantFiled: January 18, 2023Date of Patent: January 23, 2024Assignee: HRL LABORATORIES, LLCInventors: Chan-Tang Tsen, Donald Hitko, Susan Morton
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Patent number: 11588482Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.Type: GrantFiled: November 1, 2021Date of Patent: February 21, 2023Assignee: HRL LABORATORIES, LLCInventors: Chan-Tang Tsen, Donald Hitko, Susan Morton
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Patent number: 7667515Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.Type: GrantFiled: May 31, 2008Date of Patent: February 23, 2010Assignee: HRL Laboratories, LLCInventors: Ken Elliott, Susan Morton, Mark Rodwell
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Patent number: 7573305Abstract: A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.Type: GrantFiled: March 3, 2008Date of Patent: August 11, 2009Assignee: HRL Laboratories, LLCInventors: Albert E. Cosand, Susan Morton
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Patent number: 7446584Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.Type: GrantFiled: September 25, 2002Date of Patent: November 4, 2008Assignee: HRL Laboratories, LLCInventors: Ken Elliott, Susan Morton, Mark Rodwell
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Publication number: 20040056698Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Ken Elliott, Susan Morton, Mark Rodwell
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Patent number: 6628167Abstract: A linearized folding amplifier circuit (30) includes a comparator (40) that has a first state and a second state, and a switched output circuit that has a pair of outputs. The non-linearity in the response of a differential transistor pair to an input signal is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween that is replicated from the differential error in the base-voltages emitter voltages of the input differential pair. The output of the circuit is the combination of the partially linearized portion from the first resistor and a linearized transconductor circuit that has an output formed in response to the differential error.Type: GrantFiled: October 23, 2002Date of Patent: September 30, 2003Assignee: The Boeing CompanyInventors: Susan Morton, Albert Cosand
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Patent number: 6250161Abstract: There is provided a monitor and method for monitoring the condition of a photoresist film on a wafer in which the phase of high frequency ultrasonic pulses reflected from the wafer/photoresist interface provides an indication of the condition of the photoresist film.Type: GrantFiled: July 16, 1998Date of Patent: June 26, 2001Assignee: Board of Trustees of the Leland Stanford Junior UniversityInventors: Butrus T. Khuri-Yakub, Susan Morton, F. Levent Degertekin
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Patent number: 6026688Abstract: There is provided a monitor and method for monitoring the condition of a photoresist film on a wafer during baking in which the phase of high frequency ultrasonic pulses reflected from the wafer/photoresist interface provides an indication of the condition of the photoresist film.Type: GrantFiled: October 3, 1997Date of Patent: February 22, 2000Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Buhrus T. Khuri-Yakub, Susan Morton, F. Levent Degertekin