Patents by Inventor Susan Stone Meredith

Susan Stone Meredith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Detecting and isolating errors occurring in data communication in a multiple processor system
    Patent number: 6151689
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: November 21, 2000
    Assignee: Tandem Computers Incorporated
    Inventors: David J. Garcia, William Patterson Bunton, John Deane Coddington, John C. Krause, Susan Stone Meredith, David P. Sonnier, William Joel Watson, Linda Ellen Zalzala
  • Fail-fast, fail-functional, fault-tolerant multiprocessor system
    Patent number: 5751932
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 12, 1998
    Assignee: Tandem Computers Incorporated
    Inventors: Robert W. Horst, William Edward Baker, Randall G. Banton, John Michael Brown, William F. Bruckert, William Patterson Bunton, Gary F. Campbell, John Deane Coddington, Richard W. Cutts, Jr., Barry Lee Drexler, Harry Frank Elrod, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Geoffrey I. Iswandhi, Douglas Eugene Jewett, Curtis Willard Jones, Jr., James Stevens Klecka, John C. Krause, Stephen G. Low, Susan Stone Meredith, Steven C. Meyers, David P. Sonnier, William Joel Watson, Patricia L. Whiteside, Frank A. Williams, Linda Ellen Zalzala
  • Interrupt message delivery identified by storage location of received interrupt data
    Patent number: 5675807
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Tandem Computers Incorporated
    Inventors: Geoffrey I. Iswandhi, William Edward Baker, William Patterson Bunton, John Deane Coddington, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Susan Stone Meredith, Stephen H. Miller, David Paul Sonnier, William Joel Watson, Frank A. Williams