Abstract: A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.

Abstract: An electronic-system for implementing decision-feedback equalization (DFE) includes a first stage including a first-amplifier. The first amplifier including an in-built adder circuit. The first amplifier being configured to charge one or more output nodes of the first amplifier to a first voltage using a summed signal based on input data and a feedback signal in response to a first-clock variation, wherein the feedback signal is a partially-regenerated analog output from a regenerating amplifier. A second stage is includes a second amplifier configured as the regenerating amplifier and connected to the one or more output nodes of the first amplifier, the second amplifier configured to amplify charged output nodes of the second stage to a second voltage in response to a second-clock variation and apply a regenerative gain to the amplified second-voltage during the second-clock variation to generate the partially-regenerated analog output.

Abstract: A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.

Abstract: Embodiments herein disclose a receiver for performing adaptive equalization of data samples, wherein the receiver comprises an adaptation circuitry and an equalizer coupled to the adaptive circuitry. The adaptive circuitry is configured to estimate a pulse response of a channel, on receiving at least one data sample over the channel, wherein the pulse response of the channel identifies an intersymbol interference (ISI) present on the received at least one data sample. The equalizer is configured to perform equalization of the received at least one data sample by cancelling the identified ISI on the received at least one data sample.

Abstract: Embodiments herein disclose a receiver for performing adaptive equalization of data samples, wherein the receiver comprises an adaptation circuitry and an equalizer coupled to the adaptive circuitry. The adaptive circuitry is configured to estimate a pulse response of a channel, on receiving at least one data sample over the channel, wherein the pulse response of the channel identifies an intersymbol interference (ISI) present on the received at least one data sample.

Abstract: Accordingly embodiments herein disclose a quarter rate speculative DFE. The quarter rate speculative DFE includes a plurality of sampler circuits connected to an input terminal. The plurality of sampler circuits are configured to sample an input signal into a plurality of data samples in parallel. A plurality of quarter rate look ahead circuit connected to the plurality of sampler circuits. The plurality of quarter rate look ahead circuit is configured to simultaneously perform an align operation and a look ahead operation on the plurality of data samples based on the different clock phases to obtain a plurality of latched outputs. A plurality of multiplexers connected to the plurality of quarter rate look ahead circuit. The plurality of multiplexers is configured to generate two speculative data streams by multiplexing respective correction coefficients of each of the plurality of latched outputs.

Abstract: An electronic-system for implementing decision-feedback equalization (DFE) includes a first stage including a first-amplifier. The first amplifier including an in-built adder circuit. The first amplifier being configured to charge one or more output nodes of the first amplifier to a first voltage using a summed signal based on input data and a feedback signal in response to a first-clock variation, wherein the feedback signal is a partially-regenerated analog output from a regenerating amplifier. A second stage is includes a second amplifier configured as the regenerating amplifier and connected to the one or more output nodes of the first amplifier, the second amplifier configured to amplify charged output nodes of the second stage to a second voltage in response to a second-clock variation and apply a regenerative gain to the amplified second-voltage during the second-clock variation to generate the partially-regenerated analog output.

Abstract: A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.

Abstract: A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.

Abstract: An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.