Abstract: Deterioration in frequency stability with time in a conventional piezoelectric oscillator using an accumulation type MOS capacitance element is improved. A P-channel transistor type or an N-channel transistor type is used as a MOS capacitance element in a variable capacitance circuit used in a piezoelectric oscillator. A bias voltage is applied between P-type or N-type extraction electrodes formed in source and drain regions and an N-type extraction electrode provided in an N-well region or a P-type extraction electrode provided in a P-well region. Instability in the MOS capacitance element with time is thus eliminated.

Abstract: An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+ diffusion regions are connected to a ground potential wiring. Further, an n+ diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+ diffusion regions absorb positive holes serving as minority carriers from a channel region.

Abstract: Deterioration in frequency stability with time in a conventional piezoelectric oscillator using an accumulation type MOS capacitance element is improved. A P-channel transistor type or an N-channel transistor type is used as a MOS capacitance element in a variable capacitance circuit used in a piezoelectric oscillator. A bias voltage is applied between P-type or N-type extraction electrodes formed in source and drain regions and an N-type extraction electrode provided in an N-well region or a P-type extraction electrode provided in a P-well region. Instability in the MOS capacitance element with time is thus eliminated.

Abstract: A P type substrate is provided on a surface thereof with varactor elements. The varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film is formed on the N well, with a polysilicon layer formed further thereon. On the other hand, the varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film, greater than the gate insulating film in thickness, is formed on the N well. The polysilicon layer is then formed on the gate insulating film. Furthermore, the polysilicon layer is connected to a gate terminal, while the N well is connected to an S/D terminal via N+ diffusion layers.

Abstract: First and second varactors are disposed on a surface of a P-type substrate. The first varactor includes an N well disposed in the surface of the P-type substrate, a gate insulator disposed on the N well, and an N-type polysilicon layer disposed on the gate insulator. The second varactor includes an N well disposed in the surface of the P-type substrate, a gate insulator disposed on the N well, and a P-type polysilicon layer disposed on the gate insulator. The N-type polysilicon layer and P-type polysilicon layer are connected to a gate terminal. The N wells are connected to an SD terminal via P+ diffusion layers. The N-type polysilicon layer and P-type polysilicon layer have different work functions.

Abstract: An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+ diffusion regions are connected to a ground potential wiring. Further, an n+ diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+ diffusion regions absorb positive holes serving as minority carriers from a channel region.

Abstract: A P type substrate is provided on a surface thereof with varactor elements. The varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film is formed on the N well, with a polysilicon layer formed further thereon. On the other hand, the varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film, greater than the gate insulating film in thickness, is formed on the N well. The polysilicon layer is then formed on the gate insulating film. Furthermore, the polysilicon layer is connected to a gate terminal, while the N well is connected to an S/D terminal via N+ diffusion layers.

Abstract: First and second varactors are disposed on a surface of a P-type substrate. The first varactor includes an N well disposed in the surface of the P-type substrate, a gate insulator disposed on the N well, and an N-type polysilicon layer disposed on the gate insulator. The second varactor includes an N well disposed in the surface of the P-type substrate, a gate insulator disposed on the N well, and a P-type polysilicon layer disposed on the gate insulator. The N-type polysilicon layer and P-type polysilicon layer are connected to a gate terminal. The N wells are connected to an SD terminal via P+ diffusion layers. The N-type polysilicon layer and P-type polysilicon layer have different work functions.

Abstract: The equivalent circuit is constructed such that a gate terminal is connected to a gate electrode of a P-channel MOS transistor as a varactor and a fixed capacitor is connected between a substrate terminal having a substrate potential and the gate terminal. In addition, source and drain of the P-channel MOS transistor are commonly connected to a source/drain terminal to have the same potential and a first voltage source is connected between the source/drain terminal and the substrate terminal so that the substrate terminal is connected to the positive terminal of the first voltage source. Accordingly, employment of the equivalent circuit of the present invention allows the simulation of the C-V characteristic curve of a voltage-controlled variable capacitive element as an actual device with extremely high accuracy.

Abstract: According to an image sensor disclosed, a pixel circuit includes a photo-diode 14 for generating a photo-electric conversion voltage which corresponds to an input optical level, a transistor 11 which is activated in response to a Reset signal RST, to initialize the photo-diode 14 from a power supply VDD, a transistor 12 which, when connected between the power supply VDD and a bit line BL, amplifies a photo-electric conversion voltage and outputs it onto the bit line BL, and a transistor 13 which is activated by a word-line readout control signal WL, to interconnect the transistor 12 and the bit line BL, in which the transistor 11 is of a depletion type.

Abstract: There is disclosed an image sensor wherein the dispersion in threshold voltages of a transistor constituting a source follower for outputting a signal is compensated. The disclosed image sensor is provided with a coupling capacitor to which an output voltage of a pixel is applied through a transistor and with a transistor of a source follower to read out a voltage at the node S/Hn of the coupling capacitor.

Abstract: There is disclosed a black-level signal generation circuit for use with a CMOS-based active pixel image sensor. This black-level signal generation circuit delivers a black-level signal of a constant level at all times. The black-level signal generation circuit is equivalent in circuit configuration to any one of pixels forming an effective pixel array and any one of readout portions for reading out signals from the pixels. A photodiode is maintained in a reset state. MOS transistors whose corresponding MOS transistors are turned ‘ON/OFF’ in any one of the pixels and any one of the readout portions are all kept in ‘ON’ state. Thus, the black-level signal generation circuit can constantly produce a black-level signal equivalent in level to the pixel signal delivered when no light is incident on the effective pixels.

Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

Abstract: A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side.

Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

Abstract: There is disclosed a black-level signal generation circuit for use with a CMOS-based active pixel image sensor. This black-level signal generation circuit delivers a black-level signal of a constant level at all times. The black-level signal generation circuit is equivalent in circuit configuration to any one of pixels forming an effective pixel array and any one of readout portions for reading out signals from the pixels. A photodiode is maintained in a reset state. MOS transistors whose corresponding MOS transistors are turned ‘ON/OFF’ in any one of the pixels and any one of the readout portions are all kept in ‘ON’ state. Thus, the black-level signal generation circuit can constantly produce a black-level signal equivalent in level to the pixel signal delivered when no light is incident on the effective pixels.

Abstract: A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side.

Abstract: In a semiconductor integrated circuit, a control transistor 4 and a potential clamp circuit 9 are arranged between a power supply line 2 and a virtual power supply line 3. Even in a sleeve mode where the control transistor 4 is turned off, the potential clamp circuit 9-1 clamps the virtual power supply line 3 at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor 4 can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.

Abstract: In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode. A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode.