Patents by Inventor Susumu Watanabe

Susumu Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7140411
    Abstract: A pneumatic tire, wherein at least one peripheral main groove (2) is provided in a tread center area and inclined main grooves (3) inclined diagonal-outward in a direction reverse to the specified rotating direction of the tire and reverse inclined main grooves (4) inclined diagonal-outward in a direction reverse to the inclination direction of the inclined main grooves are disposed on both sides of the peripheral main groove alternately in the circumferential direction of the tire, the inner ends of the inclined main grooves (3) are connected midway to the reverse inclined main grooves (4) in the area of 10 to 20% of a contact width from a tire center and the outer ends thereof are extended to shoulders, and the inner ends of the reverse inclined main grooves (4) are connected to the peripheral main groove (2) and the outer ends thereof are connected midway to the inclined main grooves (3).
    Type: Grant
    Filed: November 28, 2002
    Date of Patent: November 28, 2006
    Assignee: The Yokohama Rubber Co., Ltd.
    Inventor: Susumu Watanabe
  • Publication number: 20060190921
    Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.
    Type: Application
    Filed: May 2, 2006
    Publication date: August 24, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Sachiko KOBAYASI, Toshiba KOTANI, Satoshi TANAKA, Susumu WATANABE, Mitsuhiro YANO
  • Patent number: 7065739
    Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sachiko Kobayashi, Toshiya Kotani, Satoshi Tanaka, Susumu Watanabe, Mitsuhiro Yano
  • Patent number: 6993728
    Abstract: An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing the data in parallel, take a first construction of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells, then creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group, and take a second construction of restoring a non-overlapped array data region left by excluding a data region having overlapped data from an array data region containing array data among pieces of integrat
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Watanabe
  • Patent number: 6907596
    Abstract: A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the corre
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sachiko Kobayashi, Toshiya Kotani, Satoshi Tanaka, Susumu Watanabe
  • Publication number: 20040238091
    Abstract: A pneumatic tire, wherein at least one peripheral main groove (2) is provided in a tread center area and inclined main grooves (3) inclined diagonal-outward in a direction reverse to the specified rotating direction of the tire and reverse inclined main grooves (4) inclined diagonal-outward in a direction reverse to the inclination direction of the inclined main grooves are disposed on both sides of the peripheral main groove alternately in the circumferential direction of the tire, the inner ends of the inclined main grooves (3) are connected midway to the reverse inclined main grooves (4) in the area of 10 to 20% of a contact width from a tire center and the outer ends thereof are extended to shoulders, and the inner ends of the reverse inclined main grooves (4) are connected to the peripheral main groove (2) and the outer ends thereof are connected midway to the inclined main grooves (3).
    Type: Application
    Filed: March 11, 2004
    Publication date: December 2, 2004
    Inventor: Susumu Watanabe
  • Patent number: 6789250
    Abstract: A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Watanabe, Mitsuhiro Yano
  • Patent number: 6782344
    Abstract: A sign of abnormality of a valve apparatus during its operation is grasped, an abnormal position and a portion requiring repair are specified, a range of inspection of an electric valve is limited and the degree of the sign of abnormality is judged without touching at all the valve apparatus. A driving force sensor provided to a driving portion of a valve apparatus is connected to a diagnosing apparatus, an energy sensor for detecting feed energy to the driving portion and a vibration sensor for detecting vibration of the valve apparatus are provisionally fitted to the valve apparatus. A data conversion unit converts the detection signals outputted from these three kinds of sensors to predetermined signals.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 24, 2004
    Assignee: Japan Atomic Power Co.
    Inventors: Haruo Ito, Susumu Watanabe, Tomoaki Sumita
  • Publication number: 20030188288
    Abstract: A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the corre
    Type: Application
    Filed: March 12, 2003
    Publication date: October 2, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Sachiko Kobayashi, Toshiya Kotani, Satoshi Tanaka, Susumu Watanabe
  • Patent number: 6612259
    Abstract: The present invention provides an effective oxygen generating materials, carbon dioxide absorbing materials, and transport system and transport method of live fishery products for use upon transporting live fishery products. An oxygen generating materials of the present invention is prepared by packaging solid peroxide and peroxide decomposition catalyst with a moisture-permeable material having a cup method moisture permeability (40° C., 90% RH) of more than 20 g/m2/24 hr and being impervious to water at normal pressure. Furthermore, a carbon dioxide absorbing materials are prepared by packaging alkaline earth metal hydroxide and/or oxide with a gas-permeable material having a Gurley method gas permeability (JIS P8117) of 0.1˜3000 sec./100 ml of gas and being impervious to water at normal pressure.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: September 2, 2003
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kiyoshi Yoshida, Yasuo Hiro, Jun Kokubo, Chiharu Nishizawa, Susumu Watanabe
  • Publication number: 20030126582
    Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Inventors: Sachiko Kobayashi, Toshiya Kotani, Satoshi Tanaka, Susumu Watanabe, Mitsuhiro Yano
  • Publication number: 20030088839
    Abstract: An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing the data in parallel, take a first construction of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells, then creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group, and take a second construction of restoring a non-overlapped array data region left by excluding a data region having overlapped data from an array data region containing array data among pieces of integrat
    Type: Application
    Filed: December 20, 2002
    Publication date: May 8, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Susumu Watanabe
  • Patent number: 6541358
    Abstract: A semiconductor device fabrication method of the present invention includes: a step of forming an insulation film on a semiconductor substrate on which a plurality of gate electrodes are formed; a step of applying SOG of HSQ type on the insulation film; a first firing step of firing the resulting substrate at a first temperature in nitrogen atmosphere; a step of forming an oxide film on the SOG of the HSQ type by a CVD method; a step of forming contact holes to expose the semiconductor substrate by removing the insulation film and the SOG of the HSQ type and the oxide film in the regions among a plurality of the gate electrodes; and a second firing step of firing the resulting substrate after the first contact hole formation at a second temperature higher than the first temperature.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: April 1, 2003
    Assignee: NEC Corporation
    Inventor: Susumu Watanabe
  • Patent number: 6543039
    Abstract: An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing the data in parallel, take a first construction of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells, then creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group, and take a second construction of restoring a non-overlapped array data region left by excluding a data region having overlapped data from an array data region containing array data among pieces of integrat
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: April 1, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Watanabe
  • Publication number: 20030009739
    Abstract: A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.
    Type: Application
    Filed: July 8, 2002
    Publication date: January 9, 2003
    Inventors: Susumu Watanabe, Mitsuhiro Yano
  • Patent number: 6481002
    Abstract: An LSI mask writing data compressing system and method according to the present invention generates first-coordinate-axial one-dimensional arrays for each individual layout pattern, each of which comprises individual layout patterns having the same shape repeatedly arranged at regular intervals in the direction of a first coordinate axis, second-coordinate-axial one-dimensional arrays for each individual layout pattern, each of which comprises individual layout patterns having the same shape repeatedly arranged at regular intervals in the direction of a second coordinate axis perpendicular to the first coordinate axis, two-dimensional arrays for each individual layout pattern, each of which comprises first-coordinate-axial one-dimensional arrays for each individual layout pattern repeatedly arranged at regular intervals in the direction of the second coordinate direction, a first-coordinate-axial block array of multiple layout patterns, which comprises grouped first-coordinate-axial one-dimensional arrays for
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: November 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Watanabe
  • Publication number: 20020095986
    Abstract: A sign of abnormality of a valve apparatus during its operation is grasped, an abnormal position and a portion requiring repair are specified, a range of inspection of an electric valve is limited and the degree of the sign of abnormality is judged without touching at all the valve apparatus. A driving force sensor provided to a driving portion of a valve apparatus is connected to a diagnosing apparatus, an energy sensor for detecting feed energy to the driving portion and a vibration sensor for detecting vibration of the valve apparatus are provisionally fitted to the valve apparatus. A data conversion unit converts the detection signals outputted from these three kinds of sensors to predetermined signals.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 25, 2002
    Applicant: Japan Atomic Power Co. &
    Inventors: Haruo Ito, Susumu Watanabe, Tomoaki Sumita
  • Publication number: 20020052108
    Abstract: A semiconductor device fabrication method of the present invention includes: a step of forming an insulation film on a semiconductor substrate on which a plurality of gate electrodes are formed; a step of applying SOG of HSQ type on the insulation film; a first firing step of firing the resulting substrate at a first temperature in nitrogen atmosphere; a step of forming an oxide film on the SOG of the HSQ type by a CVD method; a step of forming contact holes to expose the semiconductor substrate by removing the insulation film and the SOG of the HSQ type and the oxide film in the regions among a plurality of the gate electrodes; and a second firing step of firing the resulting substrate after the first contact hole formation at a second temperature higher than the first temperature.
    Type: Application
    Filed: October 16, 2001
    Publication date: May 2, 2002
    Applicant: NEC Corporation
    Inventor: Susumu Watanabe
  • Publication number: 20020001548
    Abstract: The present invention provides an effective oxygen generating materials, carbon dioxide absorbing materials, and transport system and transport method of live fishery products for use upon transporting live fishery products. An oxygen generating materials of the present invention is prepared by packaging solid peroxide and peroxide decomposition catalyst with a moisture-permeable material having a cup method moisture permeability (40° C., 90% RH) of more than 20 g/m2/24 hr and being impervious to water at normal pressure. Furthermore, a carbon dioxide absorbing materials are prepared by packaging alkaline earth metal hydroxide and/or oxide with a gas-permeable material having a Gurley method gas permeability (JIS P8117) of 0.1˜3000 sec./100 ml of gas and being impervious to water at normal pressure.
    Type: Application
    Filed: August 7, 2001
    Publication date: January 3, 2002
    Inventors: Kiyoshi Yoshida, Yasuo Hiro, Jun Kokubo, Chiharu Nishizawa, Susumu Watanabe
  • Patent number: D475010
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: May 27, 2003
    Assignee: The Yokohama Rubber Co., Ltd.
    Inventors: Sadakazu Takei, Susumu Watanabe, Masashi Wakatsuki