Patents by Inventor Suvansh K. Kapur

Suvansh K. Kapur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6912612
    Abstract: A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: June 28, 2005
    Assignee: Intel Corporation
    Inventors: Suvansh K. Kapur, Kai Cheng, Robert J. Hoogland
  • Publication number: 20030163649
    Abstract: A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.
    Type: Application
    Filed: February 5, 2003
    Publication date: August 28, 2003
    Inventors: Suvansh K. Kapur, Kai Cheng, Robert J. Hoogland
  • Patent number: 5613071
    Abstract: A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: March 18, 1997
    Assignee: Intel Corporation
    Inventors: Linda J. Rankin, Joseph Bonasera, Nitin Y. Borkar, Linda C. Ernst, Suvansh K. Kapur, Daniel A. Manseau, Frank Verhoorn