Patents by Inventor Suzanne Granato
Suzanne Granato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8935586Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.Type: GrantFiled: November 8, 2012Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Valarie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette, Nancy H. Pratt, Michael A. Ziegerhofer
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Publication number: 20140129888Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.Type: ApplicationFiled: November 8, 2012Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette, Nancy H. Pratt, Michael A. Ziegerhofer
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Patent number: 8612813Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.Type: GrantFiled: January 25, 2013Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette
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Patent number: 8452566Abstract: An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.Type: GrantFiled: May 2, 2008Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Kenneth J. Goodnow, Suzanne Granato, Eze Kamanu, Todd E. Leonard, Ramnath Ravindran, Kyle E. Schneider, Peter A. Twombly
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Patent number: 8407633Abstract: A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration.Type: GrantFiled: October 26, 2009Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Adam J. Courchesne, Jonathan P. Ebbers, Kenneth J. Goodnow, Suzanne Granato, Eze Kamanu, Kyle E. Schneider, Peter A. Twombly
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Patent number: 8381052Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.Type: GrantFiled: November 10, 2009Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette
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Patent number: 8103998Abstract: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.Type: GrantFiled: February 20, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Jesse E. Craig, Suzanne Granato, Francis A. Kampf, Barbara L. Powers
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Publication number: 20110113280Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.Type: ApplicationFiled: November 10, 2009Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Valerie H. CHICKANOSKY, Kevin W. GORMAN, Suzanne GRANATO, Michael R. OUELLETTE
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Publication number: 20110099527Abstract: A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Applicant: International Business Machines CorporationInventors: Adam J. Courchesne, Johnathan P. Ebbers, Kenneth J. Goodnow, Suzanne Granato, Eze Kamanu, Kyle E. Schneider, Peter A. Twombly
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Patent number: 7831879Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.Type: GrantFiled: February 19, 2008Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Bruce J. Ditmyer, Susan Farmer Bueti, Jonathan P. Ebbers, Suzanne Granato, Francis A. Kampf, Barbara L. Powers, Louis Stermole
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Publication number: 20090276178Abstract: An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.Type: ApplicationFiled: May 2, 2008Publication date: November 5, 2009Inventors: Kenneth J. Goodnow, Suzanne Granato, Eze Kamanu, Todd E. Leonard, Ramnath Ravindran, Kyle E. Schneider, Peter A. Twombly
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Publication number: 20090276232Abstract: An integrated circuit (IC) including a warranty and enforcement system and a method are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.Type: ApplicationFiled: May 2, 2008Publication date: November 5, 2009Inventors: Kenneth J. Goodnow, Suzanne Granato, Eze Kamanu, Todd E. Leonard, Ramnath Ravindran, Kyle E. Schneider, Peter A. Twombly
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Publication number: 20090210837Abstract: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.Type: ApplicationFiled: February 20, 2008Publication date: August 20, 2009Inventors: Jesse E. Craig, Suzanne Granato, Francis A. Kampf, Barbara L. Powers
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Publication number: 20090210746Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.Type: ApplicationFiled: February 19, 2008Publication date: August 20, 2009Inventors: Bruce J. Ditmyer, Susan Farmer Bueti, Jonathan P. Ebbers, Suzanne Granato, Francis A. Kampf, Barbara L. Powers, Louis Stermole
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Patent number: 7360138Abstract: A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is created for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.Type: GrantFiled: February 23, 2006Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Jesse Ethan Craig, Suzanne Granato, Francis A. Kampf, Barbara L. Powers
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Publication number: 20070220386Abstract: A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is crated for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.Type: ApplicationFiled: February 23, 2006Publication date: September 20, 2007Inventors: Jesse Ethan Craig, Suzanne Granato, Francis A. Kampf, Barbara L. Powers
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Patent number: 7251794Abstract: A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.Type: GrantFiled: October 21, 2004Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Rafael Blanco, Suzanne Granato, Francis A. Kampf, Douglas T. Massey
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Publication number: 20060090149Abstract: A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.Type: ApplicationFiled: October 21, 2004Publication date: April 27, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rafael Blanco, Suzanne Granato, Francis Kampf, Douglas Massey
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Publication number: 20050265462Abstract: A method for managing power consumptions of a sending driver and a receiving driver within a data communication system is disclosed. The sending driver is coupled to a sender and a sensor. The receiving driver is coupled to a receiver and a controller. The sensor adjusts a transmission frequency and a supply voltage level to the sending driver according to the amount of data that needed to be sent by the sender. Data within the sender are then transmitted by the sending driver to the receiving driver according to the adjusted transmission frequency and the adjusted supply voltage level.Type: ApplicationFiled: May 28, 2004Publication date: December 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Serafino Bueti, Kai Feng, Suzanne Granato, Allen Haar, Anthony Perri, Hemen Shah