Patents by Inventor Suzanne M Hughes

Suzanne M Hughes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6877145
    Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: April 5, 2005
    Assignee: 3Com Corporation
    Inventors: Sean Boylan, Derek Coburn, Tadhg Creedon, Denise De Paor, Vincent Gavin, Kevin J Hyland, Suzanne M Hughes, Kevin Jennings, Mike Lardner, Brendan Walsh
  • Patent number: 6718411
    Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 6, 2004
    Assignee: 3Com Corporation
    Inventors: Tadhg Creedon, Vincent Gavin, Denise de Paor, Kevin J Hyland, Kevin Jennings, Derek Coburn, Mike Lardner, Suzanne M Hughes, Sean Boylan, Brendan Walsh
  • Patent number: 6552590
    Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: April 22, 2003
    Assignee: 3Com Corporation
    Inventors: Susan M Pratt, Vincent Gavin, Tadhg Creedon, Suzanne M Hughes, Mike Lardner, Padraic O'Reilly
  • Publication number: 20020184453
    Abstract: A data bus system in which a read or write transaction includes an identification of the initiator of the transaction and optionally an identification of the transaction as a number in a cyclic progression and optionally a request for an acknowledgement.
    Type: Application
    Filed: June 29, 2001
    Publication date: December 5, 2002
    Inventors: Suzanne M. Hughes, Tadhg Creedon, Denise De Paor, Vincent Gavin, Kevin J. Hyland, Kevin Jennings, Mike Lardner, Derek Coburn
  • Publication number: 20020184419
    Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths
    Type: Application
    Filed: June 29, 2001
    Publication date: December 5, 2002
    Inventors: Tadhg Creedon, Vincent Gavin, Denise De Paor, Kevin J. Hyland, Kevin Jennings, Derek Coburn, Mike Lardner, Suzanne M. Hughes, Sean Boylan, Brendan Walsh
  • Publication number: 20020140457
    Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronisers
    Type: Application
    Filed: June 13, 2001
    Publication date: October 3, 2002
    Inventors: Susan M. Pratt, Vincent Gavin, Tadhg Creedon, Suzanne M. Hughes, Mike Lardner, Padraic O'Reilly