Abstract: The present invention includes a method of forming a capacitor on a semiconductor support wafer. The method comprises forming a diffusion area in the support wafer to provide a first electrode and a second electrode of the capacitor, implanting a first gas in the diffusion area to form a dielectric layer at a predetermined depth, wherein a first region of the diffusion area is formed below the dielectric layer as the first electrode of the capacitor and a second region of the diffusion area is formed above the dielectric layer as the second electrode of the capacitor, etching a trench in the support wafer to isolate laterally the dielectric layer, growing an epitaxial layer, and implanting a second gas to isolate the epitaxial layer from the second electrode. The capacitor is formed substantially subjacent a semiconductor device formed in the epitaxial layer.

Abstract: A method of forming a submerged semiconductor structure is provided. According to one embodiment, a recessed area is formed on the surface of a wafer of first conductivity type. A dielectric layer is then formed on the surface of the wafer and recessed area. Polysilicon may then deposited in the recessed area to form a polysilicon region, and a dopant of second conductivity type may be selectively implanted in a first defined region. An epitaxial layer may then be grown over the structure. In one embodiment, the first defined region may pattern the implantation of the dopant to form a submerged transistor. In another embodiment, a second region under the recessed area is also implanted with a dopant of second conductivity type, and the first defined region may control the selective implantation to form a submerged capacitor.

Abstract: A capacitor memory data storage system of reading, writing and refreshing which uses short bit line segments separated by pass transistors to allow smaller capacitors and faster speeds than the prior art.

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A DRAM that has an amplifier built into the cell, which gives the same output signal on the read bit line regardless of the size of the storage capacitor. The memory includes short bit line segments in the refresh mode with the provision of interconnecting the segments in the data input and output modes, where each bit line segment includes a separate amplifier circuit.

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does-not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.

Abstract: A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.

Abstract: A multilevel semiconductor integrated circuit is fabricated by providing a plurality of substrates having an epitaxial layer on one surface and a silicon oxide layer on the surface of the epitaxial layer. The substrates are sequentially stacked with the silicon oxide layers in contact and fused together. One substrate is retained as a support, and other substrates are removed by etching after the fusion of the silicon oxide layers, thereby leaving only the stacked epitaxial layers separated by silicon oxide. The stacked structure facilitates the vertical fabrication of CMOS transistor pairs sharing a common gate electrode in an epitaxial layer between the two transistors. Electrical isolation between the epitaxial layers is provided by the fused silicon oxide or by removing the silicon oxide and some of the silicon thereby forming a void between adjacent epitaxial layers. Circuit devices in the plurality of epitaxial layers are readily interconnected by forming conductive vias between the epitaxial layers.

Abstract: A sprinkler system including a controller having a manual data entry device, a processor and a sprinkler controller. Data is entered through the data entry means relating to conditions in each of a number of zones in which sprinkling is to occur with respect to the amount of water needed to be applied to that zone and the soil water infiltration rate. Upon receiving this information, the processor determines for each zone the number of cycles and the length of time in each cycle that water is to be applied not only so that the amount of water applied during each cycle does not exceed the amount of water the soil can absorb during that cycle, but also so that the total amount of water needed by that zone is applied. The processor employs the number of cycles and the length of on time per cycle to organize the cycles for all of the zones, creating an application program.

Abstract: Method and apparatus for electrostatically generating power by converting random mechanical motion into electrical energy. The apparatus includes two variable capacitors that have their capacitances varied in an alternating manner by the physical displacement of a common conductor that forms one plate in each of the capacitors. The variable capacitors are formed in a container which holds a fluid for increasing the output power of the apparatus. The fluid in combination with movable conductor also generates sufficient charge to bias the variable capacitors.

Abstract: Method and apparatus for charging a battery or other electrical energy storage means by converting random mechanical motion into electrical energy by utilizing gravitational and acceleration forces. The apparatus includes two variable capacitors and a bias supply connected to the battery or electrical energy storage means. The variable capacitors have their capacitance varied in an alternating manner by the physical displacement of a conductive member that forms one plate in each of the capacitors. The moving conductive member causes the electrical charge on the capacitors to be passed back and forth. The apparatus further includes a plurality of diodes located in the circuit so that each time the electrical charge passes between the capacitors the current formed thereby passes through the battery and charges it.

Abstract: A system for detecting passive resonant circuits in which bursts of swept radio frequency are transmitted to excite passive resonant circuits. If a circuit is resonant at a particular burst frequency, it is excited, rings and emits a radio frequency signal. Following each transmitted burst, a receiver is turned on to receive energy emitted by a resonant circuit so that if a resonant circuit is excited, its emitted energy is received and the particular resonant circuit identified.