Patents by Inventor Sven Hosp

Sven Hosp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories
    Patent number: 9646716
    Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C).
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Michael Goessel, Sven Hosp, Guenther Niess, Klaus Oberlaender
  • Circuit arrangement and method for realizing check bit compacting for cross parity codes
    Patent number: 9645883
    Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Sven Hosp, Michael Goessel, Klaus Oberlaender
  • CIRCUIT ARRANGEMENT AND METHOD FOR REALIZING CHECK BIT COMPACTING FOR CROSS PARITY CODES
    Publication number: 20150089333
    Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Sven Hosp, Michael Goessel, Klaus Oberlaender
  • CIRCUIT ARRANGEMENT AND METHOD WITH MODIFIED ERROR SYNDROME FOR ERROR DETECTION OF PERMANENT ERRORS IN MEMORIES
    Publication number: 20150039952
    Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C).
    Type: Application
    Filed: July 31, 2014
    Publication date: February 5, 2015
    Inventors: Michael Goessel, Sven Hosp, Guenther Niess, Klaus Oberlaender