Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Abstract: By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Abstract: A first trench and a second trench, both extending from a main surface into a semiconductor layer, are filled with a first fill material. The first fill material is selectively recessed in the first trench. A mask is formed that covers the second trench and that exposes the first trench. An oxidation rate promoting material is implanted into an exposed first section of the recessed fill material in the first trench. The mask is removed. Then the first fill material is thermally oxidized, wherein on the first section an oxidation rate is at least twice as high as on non-implanted sections of the first fill material.

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Abstract: By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Abstract: A first trench and a second trench, both extending from a main surface into a semiconductor layer, are filled with a first fill material. The first fill material is selectively recessed in the first trench. A mask is formed that covers the second trench and that exposes the first trench. An oxidation rate promoting material is implanted into an exposed first section of the recessed fill material in the first trench. The mask is removed. Then the first fill material is thermally oxidized, wherein on the first section an oxidation rate is at least twice as high as on non-implanted sections of the first fill material.

Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

Abstract: A trench transistor is disclosed. One embodiment has an active zone enclosed by an edge trench, wherein an edge electrode at gate potential is embedded into the edge trench, and the active zone has a mesa structure at least partly adjoining the edge trench. That region of the mesa structure which adjoins the edge trench is at least partly electrically deactivated by virtue of the fact that within this deactivated region a) the mesa structure is covered with a mesa insulation layer, and b) no source zone is provided.

Abstract: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.

Abstract: A trench transistor is disclosed. One embodiment has an active zone enclosed by an edge trench, wherein an edge electrode at gate potential is embedded into the edge trench, and the active zone has a mesa structure at least partly adjoining the edge trench. That region of the mesa structure which adjoins the edge trench is at least partly electrically deactivated by virtue of the fact that within this deactivated region a) the mesa structure is covered with a mesa insulation layer, and b) no source zone is provided.

Abstract: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.

Abstract: A semiconductor component having a vertical power transistor and at least one driver circuit for driving the vertical power transistor, and to a method for its production is disclosed. In the semiconductor component according to the invention, the layer thickness of the monocrystalline semiconductor layer in the region where the vertical power transistor is formed is less than the layer thickness of the monocrystalline semiconductor layer in the region where the driver circuit is formed. In particular, this may be achieved in that a surface region where the vertical power transistor is formed lies lower than a surface region where the driver circuit is formed. This makes it possible to reduce the on-state resistance of the semiconductor component without compromising its dielectric strength.

Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

Abstract: A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first zone, and at least one trench extending into the semiconductor body in a vertical direction through the second zone, applying a first insulation layer at least in a region of the second zone in the trench, applying a first layer of electrode material to the semiconductor body, applying an intermediate layer to the first layer, applying a second layer of electrode material to the intermediate layer, removing a portion of the second layer and of the intermediate layer to leave the intermediate layer and the second layer at least partly in the trench, and patterning the first layer.

Abstract: A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first zone, and at least one trench extending into the semiconductor body in a vertical direction through the second zone, applying a first insulation layer at least in a region of the second zone in the trench, applying a first layer of electrode material to the semiconductor body, applying an intermediate layer to the first layer, applying a second layer of electrode material to the intermediate layer, removing a portion of the second layer and of the intermediate layer to leave the intermediate layer and the second layer at least partly in the trench, and patterning the first layer.