Patents by Inventor Swaminathan (Sam) Sivakumar

Swaminathan (Sam) Sivakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sub-resolution assist features
    Patent number: 7759028
    Abstract: Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: July 20, 2010
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Swaminathan Sam Sivakumar, Paul A. Nyhus
  • SUB-RESOLUTION ASSIST FEATURES
    Publication number: 20100068633
    Abstract: Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: INTEL CORPORATION
    Inventors: CHARLES H. WALLACE, Swaminathan Sam Sivakumar, Paul A. Nyhus
  • Sub-resolution assist features
    Patent number: 7632610
    Abstract: Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: December 15, 2009
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus, Swaminathan (Sam) Sivakumar
  • Accommodating diffraction in the printing of features on a substrate
    Patent number: 7288344
    Abstract: Systems and techniques for accommodating diffraction in the printing of features on a substrate. In one implementation, a method includes identifying a pair of features to be printed using a corresponding pair of patterning elements and increasing a separation distance between the pair of patterning elements while maintaining the sufficiently small pitch between the corresponding imaged features. The pitch of the pair of features can be sufficiently small that, upon printing, diffraction will make a separation between the features smaller than a separation between the corresponding pair of patterning elements.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventors: Rex K. Frost, Swaminathan (Sam) Sivakumar
  • Multiple exposure technique to pattern tight contact geometries
    Patent number: 6968532
    Abstract: A mask pattern may be decomposed into two or more masks, each having a pitch greater than that of the original mask pattern. New, “partial-pattern” masks may be created for each of the new mask patterns. The original mask pattern is transferred to the photoresist for the corresponding layer using a multiple exposure technique in which the photoresist is exposed with each of the partial-pattern masks individually, e.g., back-to-back in a pass through a scanner, to define all of the features in the original pattern.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: November 22, 2005
    Assignee: Intel Corporation
    Inventors: Swaminathan (Sam) Sivakumar, Rex K. Frost, Phi Nguyen