Patents by Inventor Swaninathan Sivakumar

Swaninathan Sivakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9153477
    Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaninathan Sivakumar, Robert Bristol
  • Publication number: 20140091476
    Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Paul A. Nyhus, Swaninathan Sivakumar