Patents by Inventor Swapnil Bahl
Swapnil Bahl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10354742Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.Type: GrantFiled: January 31, 2017Date of Patent: July 16, 2019Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Shray Khullar
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Publication number: 20170140838Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.Type: ApplicationFiled: January 31, 2017Publication date: May 18, 2017Inventors: Swapnil Bahl, Shray Khullar
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Patent number: 9606180Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.Type: GrantFiled: May 6, 2014Date of Patent: March 28, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Swapnil Bahl, Shray Khullar
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Patent number: 9264049Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.Type: GrantFiled: November 21, 2013Date of Patent: February 16, 2016Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Shray Khullar
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Patent number: 9234938Abstract: The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.Type: GrantFiled: May 6, 2014Date of Patent: January 12, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Shray Khullar, Swapnil Bahl
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Publication number: 20150323593Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.Type: ApplicationFiled: May 6, 2014Publication date: November 12, 2015Applicant: STMicroelectronics International N.V.Inventors: Swapnil BAHL, Shray Khullar
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Publication number: 20150323594Abstract: The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.Type: ApplicationFiled: May 6, 2014Publication date: November 12, 2015Applicant: STMicroelectronics International N.V.Inventors: Shray KHULLAR, Swapnil BAHL
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Publication number: 20150137862Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Shray Khullar
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Patent number: 8917123Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.Type: GrantFiled: March 29, 2013Date of Patent: December 23, 2014Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Shray Khullar
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Publication number: 20140292385Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: STMicroelectronics International N.V.Inventors: SWAPNIL BAHL, Shray Khullar
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Patent number: 8775857Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.Type: GrantFiled: June 2, 2011Date of Patent: July 8, 2014Assignee: STMicroelectronics International N.V.Inventors: Shray Khullar, Swapnil Bahl
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Patent number: 8527824Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.Type: GrantFiled: January 11, 2013Date of Patent: September 3, 2013Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Akhil Garg
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Patent number: 8458545Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.Type: GrantFiled: November 29, 2010Date of Patent: June 4, 2013Assignee: STMicroelectronics International N.V.Inventors: Tanmoy Roy, Harsh Rawat, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria
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Patent number: 8381051Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.Type: GrantFiled: June 22, 2010Date of Patent: February 19, 2013Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Akhil Garg
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Publication number: 20120166860Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.Type: ApplicationFiled: June 2, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTDInventors: Shray Khullar, Swapnil Bahl
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Publication number: 20120137188Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.Type: ApplicationFiled: November 29, 2010Publication date: May 31, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Tanmoy Roy, Harsh Rawat, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria
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Publication number: 20110264971Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.Type: ApplicationFiled: June 22, 2010Publication date: October 27, 2011Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Swapnil Bahl, Akhil Garg
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Patent number: 7814385Abstract: A built-in self-test (BIST) device tests multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a memory test algorithm. The delay generator provides a delay of an expected data, a valid signal, a BBAD signal, a BEND signal, and a BFAIL signal. The multiple interface modules provide signal pipelining for multiple memories through a bus. The bus carries signals form the BIST device to multiple memories and vice-versa. The memory wrapper decodes a selected memory for decompressing a memory data signal generated by said BIST device and further compresses a memory output signal.Type: GrantFiled: August 30, 2007Date of Patent: October 12, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventor: Swapnil Bahl
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Patent number: 7372755Abstract: An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out (FIFO) memory, and a controller for performing operations on the memory. In operation, the memory is converted into a FIFO memory after storing data, and output logic selects data to be output in a serial manner.Type: GrantFiled: April 8, 2005Date of Patent: May 13, 2008Assignee: STMicroelectronics Pvt. Ltd.Inventors: Swapnil Bahl, Balwant Singh
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Patent number: 7353442Abstract: An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for applying specified test patterns on the associated memory array.Type: GrantFiled: April 8, 2005Date of Patent: April 1, 2008Assignee: STMicroelectronics Pvt. Ltd.Inventors: Swapnil Bahl, Balwant Singh