Abstract: A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.

Abstract: A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.

Abstract: A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

Abstract: A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.

Abstract: A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.

Abstract: A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.