Patents by Inventor Swee Kwang Chua
Swee Kwang Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8669657Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.Type: GrantFiled: August 27, 2013Date of Patent: March 11, 2014Assignee: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Publication number: 20140008784Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.Type: ApplicationFiled: August 27, 2013Publication date: January 9, 2014Applicant: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Patent number: 8564106Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: GrantFiled: January 27, 2012Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo
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Patent number: 8555495Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: November 17, 2011Date of Patent: October 15, 2013Assignee: Micron Technology, Inc.Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Patent number: 8518747Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.Type: GrantFiled: September 14, 2012Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Patent number: 8362594Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.Type: GrantFiled: March 29, 2011Date of Patent: January 29, 2013Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia
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Publication number: 20130011966Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: MICRON TECHNOLOGY, INC.Inventor: Swee Kwang Chua
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Patent number: 8288874Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies.Type: GrantFiled: December 30, 2010Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Publication number: 20120119263Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: ApplicationFiled: January 27, 2012Publication date: May 17, 2012Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo
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Publication number: 20120064697Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: ApplicationFiled: November 17, 2011Publication date: March 15, 2012Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Patent number: 8106488Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: GrantFiled: October 6, 2010Date of Patent: January 31, 2012Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Neo Yong Loo
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Patent number: 8065792Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: February 15, 2010Date of Patent: November 29, 2011Assignee: Micron Technology, Inc.Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Publication number: 20110095407Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies.Type: ApplicationFiled: December 30, 2010Publication date: April 28, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Swee Kwang Chua
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Patent number: 7915711Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.Type: GrantFiled: January 29, 2010Date of Patent: March 29, 2011Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Suan Jeung Boon, Yoon Poo Chia
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Publication number: 20110018143Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: ApplicationFiled: October 6, 2010Publication date: January 27, 2011Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Neo Yong Loo
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Patent number: 7863722Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies.Type: GrantFiled: October 20, 2008Date of Patent: January 4, 2011Assignee: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Patent number: 7820484Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: GrantFiled: May 13, 2008Date of Patent: October 26, 2010Assignee: Micron Technology, IncInventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo
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Patent number: 7816750Abstract: Thin semiconductor die packages and associated systems and methods are disclosed. A package in accordance with a particular embodiment includes a semiconductor die having die bond sites, a conductive structure positioned proximate to the semiconductor die and having first bond sites and second bond sites spaced apart from the first bond sites, and conductive couplers connected between the first bond sites of the conductive structure and the die bond sites of the semiconductor die. A cover can be positioned adjacent to the semiconductor die, and can include a recess in which the conductive couplers are received.Type: GrantFiled: September 25, 2007Date of Patent: October 19, 2010Assignee: Aptina Imaging CorporationInventor: Swee Kwang Chua
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Publication number: 20100146780Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: ApplicationFiled: February 15, 2010Publication date: June 17, 2010Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Patent number: 7712211Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: December 23, 2003Date of Patent: May 11, 2010Assignee: Micron Technology, Inc.Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua