Abstract: The present invention is directed to a frequency synthesizer with an improved architecture that eliminates a VCO and a method to build frequency synthesizers for generating high-frequency signals with low phase noise, low spurious, extremely fast switching speed and fine frequency resolution. The synthesizer provides significant improvement in performance, phase noise, switching speed, power, size and cost reduction.

Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The reference frequency source for the low phase noise loop includes a mixer/divider up-conversion chain at the output of a direct digital synthesizer. This permits fine frequency resolution from the DDS but maintains a high phase detector comparison frequency and therefore fast frequency switching speed.