Abstract: Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be transferred. A comparator compares recalled data to stored transparency data and indicates whether data to be transferred is to be written to memory. Destination address controller writes data to be transferred into memory at calculated destination addresses if the comparator indicates data to be transferred is to be written to memory. The recalled data is stored in a source register for comparison. In the preferred embodiment data is not written into memory if it matches the transparency data. The transparency register may store a multiple of the minimum amount of data to be transferred. The data to be transferred is organized into data words having a selected size. This selected size is an integral multiple of a minimum amount of data to be transferred.

Abstract: A data processor with a transparency detection data transfer controller transfers data from a block of source addresses to a block of destination addresses. A transparency register stores transparency data. A comparator compares the recalled data to the stored transparency data and indicates whether the data to be transferred is to be written to the memory. The recalled data to be transferred is not to be written into the memory if it matches the transparency data. The transparency register may store a multiple of a multibit minimum amount of data to be transferred. The data to be transferred has a selected size which is an integral multiple of a minimum amount of data to be transferred. The comparator includes plural data comparators corresponding to each multibit minimum amount of data to be transferred.

Abstract: A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table.

Abstract: An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2.sup.M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2.sup.M -1 inclusive from the most significant bits of the numerator.

Abstract: Disclosed is an electronic calculator system having an input for receiving data and command signals, a memory for storing inputted data and data to be outputted, an arithmetic unit for performing arithmetic operations on the data stored in the memory, a first read-only-memory for storing groups of instruction words for controlling the data stored within the memory and for controlling the arithmetic operations performed by the arithmetic unit, a second read-only-memory for storing a set of program codes, each program code being effective for addressing a selected group of instruction words and control circuitry for reading out the groups of instruction words corresponding to an addressed set of program codes.

Abstract: A microprocessor system with high order capabilities is provided with the two non-volatile memories which are read-only-memories (ROMs) in the disclosed embodiment. A first ROM stores the microcode for controlling the operation of the microprocessor circuits. The second ROM, which is preferably disposed in a module or cartridge, stores a plurality of program codes which are used to address the first ROM. The second ROM's module may be inserted into a receptacle for interconnecting it with the remainder of the microprocessor system. Preferably, a plurality of such second ROMs are available for selectively plugging into the microprocessor system.Further, a particular embodiment of the microprocessor system with high order capabilities for use as an electronic calculator with high order capabilities is disclosed in great detail.

Abstract: A calculator program is stored on a magnetic recording medium or in a memory such as a read-only-memory. The program is read into or coupled to a programmable calculator for controlling the programmable calculator. A calculator program security system is provided whereby a security code is stored along with the program. If the security code is set, then the program cannot be examined by an operator of the calculator but the program may still be used to control the calculator. If the security code is not set, the operator may examine the program by using the calculator's learn mode. By setting the security code when the program is first stored on the magnetic recording medium or in the aforementioned memory, a proprietary program may be protected from someone using the programmable calculator to obtain a copy of the proprietary program.

Abstract: A microprocessor system with high order capabilities is provided with the two non-volatile memories which are read-only-memories (ROMs) in the disclosed embodiment. A first ROM stores the microcode for controlling the operation of the microprocessor circuits. The second ROM, which is preferably disposed in a module or cartridge, stores a plurality of program codes which are used to address the first ROM. The second ROM's module may be inserted into a receptacle for interconnecting it with the remainder of the microprocessor system. Preferably, a plurality of such second ROMs are available for selectively plugging into the microprocessor system.Further, a particular embodiment of the microprocessor system with high order capabilities for use as an electronic calculator with high order capabilities is disclosed in great detail.