Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Abstract: Several embodiments including methods, systems, and physical computer-readable storage media are configured to multiplex a single end-point memory (EPM) structure between a HS USB interface and a SS USB interface, which includes determining whether the SS USB interface is enabled, if the SS USB interface is enabled, detecting the SS USB interface, selecting the HS USB interface, if the SS USB interface is enabled, but not detected, and multiplexing between a functionality of a HS USB device interface and a functionality of a HS USB host interface, if the SS USB interface is not enabled.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: An embodiment of the present invention is directed to a system including a memory interface logic unit for receiving memory access requests and corresponding information, a processor coupled to the memory interface logic, a plurality of pre-fetch buffers for handling memory accesses coupled to the memory interface logic unit, an arbiter logic unit for pre-fetching data into the plurality of pre-fetch buffers, a memory device for storing data coupled to the arbiter logic unit and the plurality of pre-fetch buffers, and busy detection logic for informing the arbiter logic unit of the current operation of the processor. The arbiter logic unit facilitates memory access via pre-fetch buffers of the processor and the memory in different or independent clock domains. The arbiter logic further allows random access without introducing additional latency.

Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Abstract: A method includes receiving an endpoint address and corresponding endpoint data, the endpoint address identifying a logical endpoint associated with the endpoint data, storing the endpoint data to at least one of a plurality of memory buffers corresponding to the identified logical endpoint, and transmitting the endpoint data to a destination according to the endpoint address. A peripheral device includes a logical-to-physical memory map to store an endpoint address and corresponding endpoint data received from a first device, the endpoint address to identify at least one data stream capable of transferring the endpoint data to a second device, and a service unit to retrieve the endpoint address and corresponding endpoint data from the logical-to-physical memory map, and to transfer the endpoint data to the second device in the data stream identified by the endpoint address.

Abstract: A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.

Abstract: A controller circuit provides communication paths between multiple host devices and a target device. The controller circuit includes a first host idle detection circuit that determines when a first host interface (I/F) is in an idle state, an idle state being when the first host I/F is not communicating with the controller circuit. A switch circuit can selectively enables a controllable communication path between a second host I/F and a target device I/F. A first response circuit can be coupled to the first host I/F and output predetermined responses from the first host I/F in response to communications received on the first host I/F. The first response circuit outputting a predetermined response when at least the controller circuit has enabled the controllable communication path between a second host I/F and the target device I/F and disabled the controllable communication path between the first host I/F and the target device I/F.

Abstract: A circuit and method are provided that eliminate race conditions in data storage devices. Generally, the circuit includes: (i) an input latch to which an address signal (ADD) is applied; (ii) a multiplexer (MUX) to which the ADD is coupled from the input latch and through which an output is supplied to an output latch; (iii) an address valid signal (ADV) input coupled to the output latch and to which an ADV is applied to close the output latch supplying the output to a circuit output; and (iv) a middle latch coupled between the input latch and the MUX to hold the ADD applied to the MUX until the output latch closes, independent of a change in the ADD applied to the input latch. Preferably, the circuit includes control logic configured to close the middle latch on a rising edge of ADV and reopen it when the output latch closes.