Abstract: A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset.

Abstract: The invention relates to methods and apparatus that align serial data so as to provide corresponding parallel data. The methods and apparatus search for framing patterns in demultiplexed serial data and shift the demultiplexed serial data to provide aligned parallel data. Advantageously, embodiments of the invention can operate in real time in a relatively high-frequency optical network, such as SONET. One embodiment of the invention detects a frame pattern and provides a nibble shift output. The nibble shift output is applied to another circuit, such as a phase detector or a voltage controlled oscillator, to shift the demultiplexed serial data by a nibble, i.e., four bits. Shifts of smaller increments, i.e., one bit, two bits, or three bits, are applied to the demultiplexed data within a framing circuit to allow the framing circuit to fully align the parallel data.

Abstract: The invention relates to methods and apparatus that reset integration capacitors at high frequencies to prepare the integration capacitors to store an integration result of a transition between adjacent data bits in a serial bitstream. In one embodiment of an integrating phase detector having a reset circuit, the reset circuit resets the integration capacitors, the integrating phase detector then integrates a transition of a serial bitstream with the integration capacitors, and the integrating phase detector combines the integration results of multiple integrations with a multiplier circuit. The reset circuit couples to clock phases of a control clock, such as to a voltage controlled oscillator configured to synchronize to the serial bitstream, and is configured to time the reset of the integration capacitors so as not to occur when the integrating phase detector is integrating a transition in the integration capacitors or when integration results are dumped by the multiplier circuit.

Abstract: The invention relates to methods and apparatus that advantageously provide relatively high-frequency data communication and relatively low power consumption in a low voltage differential signaling (LVDS) output buffer or driver. The LVDS output buffer includes an output resistance selected to terminate reflections from mismatched loads. Advantageously, a portion of the resistance is isolated by an emitter to base junction from a load applied to output terminals of the LVDS output buffer. A remaining portion of the resistance can thereby be reduced, advantageously allowing a reduction in power loss and reducing an amount of voltage swing at output transistors of the LVDS output buffer.

Abstract: The invention relates to methods and apparatus that selectively multiply an analog signal by zero (0), one (1), and negative one (−1) at high speeds. In one embodiment, the analog signal corresponds to an integration result of a transition from a first data bit to a second data bit in a serial data bitstream. Advantageously, the multiplier circuit is well adapted to relatively high-frequency operation by providing a balanced load to a driver circuit such that the selected multipliers of the multiplier circuit can switch in a substantially symmetrical manner. In one embodiment, the driver circuit includes a data transition identifier circuit.

Abstract: The invention relates to methods and apparatus that provide high-speed current pulses. In one embodiment, the trigger circuit provides a current sink pulse as an output. One embodiment of the trigger circuit includes a first input transistor and an output transistor that are emitter coupled to a common resistor. A collector of the first input transistor is alternating current (AC) coupled to a base of the output transistor to drive the output transistor. Advantageously, the AC coupling allows the first input transistor to powerfully drive the output transistor during logic state transitions and yet maintain a low average current. The resistor coupled to the emitter of the first input transistor and the emitter of the output transistor advantageously provides positive feedback or hysteresis feedback, thereby further enhancing the response of the trigger circuit.

Abstract: The invention relates to methods and apparatus that receive an integration result, receive logic states of data bits corresponding to the integration result, and perform a high-speed multiplication operation. Embodiments of the invention selectively multiply the integration result according to the logic states of the corresponding data bits. Advantageously, relatively large integration results corresponding to data bit transitions that do not include a change of logic states, such as logic 0 to logic 0 or logic 1 to logic 1, can be multiplied by zero (0). Relatively smaller integration results corresponding to integrations of data bit transitions including a change in logic states, such as from logic 0 to logic 1 or from logic 1 to logic 0, can be multiplied by one (1) and by negative one (−1).

Abstract: The invention relates to methods and apparatus that indicate a first logic state and a second logic state associated with consecutive bits in a serial bitstream of a relatively high-frequency network. The serial bitstream is demultiplexed to retrieve the consecutive bits, and the consecutive bits are provided as inputs to an identifier circuit. The identifier circuit receives the demultiplexed consecutive bits and indicates via balanced outputs whether consecutive bits of the serial bitstream corresponded to logic 0 to logic 0, logic 0 to logic 1, logic 1 to logic 0, or logic 1 to logic 1. The balanced outputs that indicate the logic 0 to logic 0 sequence, the logic 0 to logic 1 sequence, the logic 1 to logic 0 sequence, and the logic 1 to logic 1 sequence advantageously provide matched delays from an activation of the identifier circuit to the activation of one of the balanced outputs.

Abstract: The invention relates to phase detectors that integrate a portion of a transition between adjacent or consecutive bits of a serial bitstream in a relatively fixed window by switching currents as opposed to voltages. The phase detector can be used to synchronize a VCO clock in a PLL to a fast data bitstream used in an optical network, such as SONET. Advantageously, embodiments of a current mode phase detector switch currents, rather than voltages, to integrate the window of the serial bitstream. The current switching allows devices to operate at frequencies approaching the device's fT and can advantageously extend the phase detector's bandwidth and allow an associated transceiver to operate at higher data rates. By contrast, the conventional switching of voltage results in a delay induced by the charging of related capacitances, such as parasitic substrate capacitances, which in turn results in actual performance far below the fT of the devices.

Abstract: The invention relates to methods and apparatus that allow a comparison of phase between a clock signal and a serial bitstream. A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop.

Abstract: The invention relates to methods and apparatus that efficiently convert a single-ended input signal to a differential output signal at high speeds so that a non-inverted differential output and an inverted differential output maintain a true differential phase relationship even at relatively high frequencies of input data. A single-to-differential input buffer circuit includes multiple paths from the input signal to the differential output signals and transitions relatively quickly from a first state to a second state in response to a change in state of the input signal. An input phase-splitting stage of the single-to-differential input buffer circuit includes cross-coupled positive feedback to dramatically increase the frequency response of the phase-splitting stage.

Abstract: The invention relates to methods and apparatus that compare the frequencies of a first clock signal and a second clock signal and reliably provide an indication of whether the frequency relationship between the first clock signal and the second clock signal is within a predetermined range. In one embodiment, the first clock signal is a reference clock signal and the second clock signal is generated from a serial bitstream. The indication can be used to synchronize a voltage controlled oscillator within a phase locked loop to the reference clock signal to thereby keep the phase locked loop within a lock range of a serial bitstream from which the second clock is generated. Embodiments of the invention digitally generate a beat frequency related to a difference in speed between the first clock signal and the second clock signal. The beat frequency is synchronized, advantageously obviating the need to synchronize asynchronous counters as is conventionally done.

Abstract: A phase frequency detector in a clock multiply unit of a serial transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. The phase frequency detector produces a pair of output signals which have rising edges corresponding to rising edges of the reference clock and the internal clock respectively. The reset circuit activates a reset signal to reset the phase frequency detector when the output signals are both at logic high and continues to activate the reset signal until both of the output signals reach logic low.

Abstract: A phase alignment circuit in a serial transmitter aligns a parallel input data stream to a first transmission clock before conversion to a serial output data stream using a second transmission clock which is a multiple of the first transmission clock. The phase alignment circuit introduces less delay, i.e., the output of the phase alignment circuit lags the input of the phase alignment by a few number of clock cycles (e.g., less than 2 clock cycles). The phase alignment circuit demultiplexes the input data stream into a plurality of intermediate data streams using a plurality of multi-phase clocks referenced to a data clock and multiplexes the plurality of intermediate data streams using sequence signals referenced to the first transmission clock. The sequence signals are initialized according to a reset condition and at least one of the multi-phase clocks.

Abstract: A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset.

Abstract: A high-speed output driver produces a fast differential output signal for a serial transmitter. The output driver includes a first stage circuit which comprises a first active element to pull the first stage circuit output to a logic high and a second active element to pull the first stage circuit output to a logic low. The first active element and the second active element are controlled by complementary signals. The first stage circuit drives a second stage circuit (e.g., a current mode logic circuit) which reacts relatively quickly to signal transitions by steering substantially constant current between differential pair transistors.

Abstract: A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset.

Abstract: The invention relates to methods and apparatus that provide a low frequency data loop-back in a transceiver to advantageously provide built-in test capability with low overhead. The low frequency loop-back advantageously allows testing of a receiver and a transmitter of the transceiver through a high frequency serial interface while reducing the need to interface to a low frequency interface of the transceiver with expensive and specialized test equipment. One embodiment of the low frequency data loop-back includes a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loop-back test command. In one embodiment, a multiplexer selects between the reference clock signal and the generated clock signal.