Patents by Inventor Syed Reza Bahadur

Syed Reza Bahadur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10877350
    Abstract: Embodiments may relate to a segment driver that is to be coupled with a modulator segment of a Mach-Zehnder modulator. The segment driver may include a continuous-time linear equalizer (CTLE) incorporated within an amplifier stage of the modulator. The CTLE may be configured to identify an electrical signal that is related to an optical signal of the Mach-Zehnder modulator; reduce inter-symbol interference (ISI) of the electrical signal to generate a processed electrical signal; and output the processed electrical signal to the amplifier stage. Other embodiments may be described or claimed.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Syed S. Islam, Raghuram Narayan, Syed Reza Bahadur, Bharadwaj Parthasarathy
  • Publication number: 20190137842
    Abstract: Embodiments may relate to a segment driver that is to be coupled with a modulator segment of a Mach-Zehnder modulator. The segment driver may include a continuous-time linear equalizer (CTLE) incorporated within an amplifier stage of the modulator. The CTLE may be configured to identify an electrical signal that is related to an optical signal of the Mach-Zehnder modulator; reduce inter-symbol interference (ISI) of the electrical signal to generate a processed electrical signal; and output the processed electrical signal to the amplifier stage. Other embodiments may be described or claimed.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 9, 2019
    Applicant: Intel Corporation
    Inventors: Syed S. Islam, Raghuram Narayan, Syed Reza Bahadur, Bharadwaj Parthasarathy
  • Patent number: 9384791
    Abstract: Disclosed is a circuit architecture for cancellation of threshold voltage offsets for an array of sense amplifiers. An offset calibration controller, which may be embedded as a hard-wired circuit in the transceiver core circuits, writes the offset adjustment values to a memory-mapped interface circuit. The memory-mapped interface circuit outputs the offset adjustment values to offset adjustment circuits for the sense amplifiers. The offset adjustment circuits may utilize a body bias technique. Advantageously, the disclosed circuit architecture provides for the minimization of residual offset without sacrificing bandwidth. Other embodiments, features and advantages are also disclosed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 5, 2016
    Assignee: Altera Corporation
    Inventors: Allen K. Chan, Vishal Giridharan, Syed Reza Bahadur