Abstract: Filter circuitry is provided for use with a light detection and ranging (Lidar) device implemented using silicon photonics. The filter circuitry includes high-pass filter circuitry to receive a signal from a photodetector of the lidar device and attenuate a lower frequency portion of the signal, where the lower frequency portion of the signal is the result of optical back reflections within the lidar device.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to packages that include CPUs and PICs electrically coupled via an interconnect bridge. In embodiments, the PIC are electrically coupled with the EMIB using a fan out RDL to extend reach of the PIC electrical connectors. EICs may be electrically coupled between the PIC and the interconnect bridge. The CPUs may be CPUS, graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other processors. Other embodiments may be described and/or claimed.

Abstract: Embodiments may relate to a segment driver that is to be coupled with a modulator segment of a Mach-Zehnder modulator. The segment driver may include a continuous-time linear equalizer (CTLE) incorporated within an amplifier stage of the modulator. The CTLE may be configured to identify an electrical signal that is related to an optical signal of the Mach-Zehnder modulator; reduce inter-symbol interference (ISI) of the electrical signal to generate a processed electrical signal; and output the processed electrical signal to the amplifier stage. Other embodiments may be described or claimed.

Abstract: Methods, apparatuses, and systems are described herein to compensate for a skew effect that occurs in an optical signal generated in response to an electrical to optical (E/O) conversion of an electrical signal carrying data received from a driver. A skew control device coupled with a driver or a modulator provides a skew to the electric signal prior to E/O conversion to compensate for the skew effect. The skew may be provided by a reverse-biased p-n junction diode. Other embodiments may be described and/or claimed.

Abstract: Embodiments may relate to a segment driver that is to be coupled with a modulator segment of a Mach-Zehnder modulator. The segment driver may include a continuous-time linear equalizer (CTLE) incorporated within an amplifier stage of the modulator. The CTLE may be configured to identify an electrical signal that is related to an optical signal of the Mach-Zehnder modulator; reduce inter-symbol interference (ISI) of the electrical signal to generate a processed electrical signal; and output the processed electrical signal to the amplifier stage. Other embodiments may be described or claimed.

Abstract: Described is an apparatus which comprises: a first capacitor coupled to a first input pad; a second capacitor coupled to second input pad; a first resistor coupled to the second capacitor; a third capacitor coupled in series with the first resistor; a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and a differential amplifier coupled to the first and second capacitors and to the first and second resistors.

Abstract: Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

Abstract: Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

Abstract: Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.

Abstract: A calibration system employed for use with a resistance capacitance (RC) filter having resistors and capacitors with parasitic capacitance associated therewith. The calibration system has a digital calibration circuit receiving a time constant signal and generating, based thereon, a control word of N digital bits. The calibration system includes an analog monitor circuit having monitor capacitance assembly having a particular equivalent resistor and capacitor configuration. The analog monitor circuit generates the time constant signal and includes N switches, where each switch is controlled by one of the N bits of the control word, each switch is configured to connect or disconnect one or more capacitors of the monitor capacitor assembly thereby generating a time constant signal that represents the time constant of the RC integrated filter.

Abstract: An integrated circuit (IC) is disclosed to include a central area of the IC that is partitioned into a first section containing at least one digital circuit and a second section containing at least one analog circuit; and a guard strip (or shield) that is within the central area and that is positioned within between the digital circuit and the analog circuit. The shield or guard strip comprises of n-well and p-tap regions that separate digital and analog circuits.

Abstract: Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.