Patents by Inventor Sylvain Ouimet
Sylvain Ouimet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11211262Abstract: An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.Type: GrantFiled: January 16, 2020Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Tuhin Sinha, Steven P. Ostrander, Bhupender Singh, Sylvain Ouimet
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Publication number: 20210225665Abstract: An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Inventors: TUHIN SINHA, Steven P. Ostrander, Bhupender Singh, Sylvain Ouimet
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Patent number: 10615511Abstract: A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements.Type: GrantFiled: March 29, 2019Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Jean Labonte, Sylvain Ouimet
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Patent number: 10374322Abstract: A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements.Type: GrantFiled: November 8, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Jean Labonte, Sylvain Ouimet
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Publication number: 20190229433Abstract: A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: Jean Labonte, Sylvain Ouimet
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Publication number: 20190140361Abstract: A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Inventors: Jean Labonte, Sylvain Ouimet
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Patent number: 9793232Abstract: A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.Type: GrantFiled: January 5, 2016Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Luc Guerin, Sylvain Ouimet, Sylvain Pharand, Thomas A. Wassick
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Patent number: 9219051Abstract: A clamping apparatus and method for applying a force to a workpiece during processing includes a base defining a work area. The work area is configured to receive a joined structure including a substrate and a die. A component is positionable in the work area and over the joined structure. An adjustable releasable structure is positionable over the component and the joined structure and includes a resilient mechanism having an inner member for contacting the component to apply an inner downward force to the component. The resilient mechanism also includes outer members for applying an outer downward force to opposing distal edge areas of the substrate. An external downward force is applied to the adjustable releasable structure, such that the inner and outer members apply the inner and outer downward forces to the component and the opposing distal edge areas of the substrate, respectively, during processing of the joined structure.Type: GrantFiled: June 5, 2013Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Stephanie Allard, Martin Beaumier, Jean-Francois Drapeau, Jean Labonte, Steven P. Ostrander, Sylvain Ouimet
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Publication number: 20140359996Abstract: A clamping apparatus and method for applying a force to a workpiece during processing includes a base defining a work area. The work area is configured to receive a joined structure including a substrate and a die. A component is positionable in the work area and over the joined structure. An adjustable releasable structure is positionable over the component and the joined structure and includes a resilient mechanism having an inner member for contacting the component to apply an inner downward force to the component. The resilient mechanism also includes outer members for applying an outer downward force to opposing distal edge areas of the substrate. An external downward force is applied to the adjustable releasable structure, such that the inner and outer members apply the inner and outer downward forces to the component and the opposing distal edge areas of the substrate, respectively, during processing of the joined structure.Type: ApplicationFiled: June 5, 2013Publication date: December 11, 2014Inventors: Stephanie Allard, Martin Beaumier, Jean-Francois Drapeau, Jean Labonte, Steven P. Ostrander, Sylvain Ouimet
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Patent number: 8559474Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.Type: GrantFiled: September 5, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Paul S. Andry, Russell A. Budd, Bing Dang, David Danovitch, Benjamin V. Fasano, Paul Fortier, Luc Guerin, Frank F. Libsch, Sylvain Ouimet, Chrirag S. Patel
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Patent number: 8421217Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.Type: GrantFiled: March 14, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Jon A. Casey, John S. Corbin, Jr., David Danovitch, Isabelle Depatie, Virendra R. Jadhav, Roger A. Liptak, Kenneth C. Marston, Jennifer V. Muncy, Sylvain Ouimet, Eric Salvas
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Publication number: 20120326290Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.Type: ApplicationFiled: September 5, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, Russell A. Budd, Bing Dang, David Danovitch, Benjamin V. Fasano, Paul Fortier, Luc Guerin, Frank R. Libsch, Sylvain Ouimet, Chrirag S. Patel
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Patent number: 8290008Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.Type: GrantFiled: August 20, 2009Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Paul S. Andry, Russell A. Budd, Bing Dang, David Danovitch, Benjamin V. Fasano, Paul Fortier, Luc Guerin, Frank R. Libsch, Sylvain Ouimet, Chirag S. Patel
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Publication number: 20120175766Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.Type: ApplicationFiled: March 14, 2012Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jon A. Casey, John S. Corbin, JR., David Danovitch, Isabelle Dépatie, Virendra R. Jadhav, Roger A. Liptak, Kenneth C. Marston, Jennifer V. Muncy, Sylvain Ouimet, Eric Salvas
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Patent number: 8202765Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.Type: GrantFiled: January 22, 2009Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Jon A. Casey, John S. Corbin, Jr., David Danovitch, Isabelle Depatie, Virendra R. Jadhav, Roger A. Liptak, Kenneth C. Marston, Jennifer V. Muncy, Sylvain Ouimet, Eric Salvas
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Publication number: 20110044369Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.Type: ApplicationFiled: August 20, 2009Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, Russell A. Budd, Bing Dang, David Danovitch, Benjamin V. Fasano, Paul Fortier, Luc Guerin, Frank R. Libsch, Sylvain Ouimet, Chirag S. Patel
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Method of Removing Metallic, Inorganic and Organic Contaminants From Chip Passivation Layer Surfaces
Publication number: 20100218894Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.Type: ApplicationFiled: May 14, 2010Publication date: September 2, 2010Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla -
Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfaces
Patent number: 7771541Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.Type: GrantFiled: March 22, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla -
Publication number: 20100181665Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.Type: ApplicationFiled: January 22, 2009Publication date: July 22, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jon A. CASEY, John S. CORBIN, JR., David DANOVITCH, Isabelle DEPATIE, Virendra R. JADHAV, Roger A. LIPTAK, Kenneth C. MARSTON, Jennifer V. MUNCY, Sylvain OUIMET, Eric SALVAS
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Method of Removing Metallic, Inorganic and Organic Contaminants from Chip Passivation Layer Surfaces
Publication number: 20080233755Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla