Patents by Inventor Syou Yanagisawa

Syou Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130286315
    Abstract: The liquid crystal display panel according to the present invention is a liquid crystal display panel LCD wherein a CF substrate S1 on which color filters are formed and a TFT substrate S2 on which thin film transistor circuits are formed are layered on top of each other with liquid crystal being sealed between the two substrates, characterized in that a black light blocking region BM is formed in a frame portion of the CF substrate S1, and an identification mark M drawn as a negative pattern is provided to a part of the light blocking region, and a metal film MT1 is provided to the TFT substrate S2 in such a location as to block light that transmits through the identification mark.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 31, 2013
    Applicant: JAPAN DISPLAY EAST INC.
    Inventor: Syou YANAGISAWA
  • Patent number: 8546812
    Abstract: A display panel includes a plurality of pads configured to provide a driver thereon, a plurality of first contacts respectively connected to the plurality of pads, a plurality of second contacts respectively provided so as to be opposed to the plurality of first contacts, a polysilicon layer configured to form a plurality of polysilicon films that are respectively extended to connect the plurality of first contacts and the plurality of second contacts to each other, and a gate metal layer different from the polysilicon layer. Each of a plurality of transistors is formed at a position where the gate metal layer traverses the polysilicon layer, and a plurality of transistor groups are arranged in a zigzag pattern. Each of the plurality of transistor groups include three adjacent transistors of the plurality of transistors.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: October 1, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Syou Yanagisawa
  • Publication number: 20130063406
    Abstract: A display device includes lead lines that extend from a display area, and electrically connect video signal lines or scanning signal lines within a display area, and a driver circuit or a terminal portion that receives an output from the driver circuit; an insulating film that is formed in an upper layer of the lead lines and covers the lead lines; and a conductive film that is formed in an upper layer of the insulating film. The lead lines include a plurality of first lead lines that start from the driver circuit or the terminal portion, and arrive at the scanning signal lines or the video signal lines, and a plurality of second lead lines that are smaller in wiring resistance than the first lead lines. At least the first lead lines overlap with the conductive film through the insulating film.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 14, 2013
    Inventors: Tomonori NISHINO, Syou YANAGISAWA, Masanari SAITOU, Yoshinori AOKI, Nobuyuki ISHIGE
  • Publication number: 20130033667
    Abstract: Provided is a liquid crystal display device capable of securing a sufficient amount of light for curing a sealing material applied to a TFT substrate side, and adjusting resistances of wirings including scanning signal lines and video signal lines. The liquid crystal display device includes: a TFT substrate (11) including a pixel electrode provided thereon; an opposing substrate (20), which is opposed to the TFT substrate (11); and a liquid crystal sealed between the TFT substrate (11) and the opposing substrate (20), in which scanning lead-out lines (31, 32) traversing a sealing material (12) for sealing the liquid crystal each include slits (23, 33) each having a shape that is open on one side formed therein along a longitudinal direction of the scanning lead-out lines (31, 32).
    Type: Application
    Filed: July 31, 2012
    Publication date: February 7, 2013
    Inventors: Syou YANAGISAWA, Tomokazu Ishikawa
  • Publication number: 20120248447
    Abstract: An electronic panel includes insulation films that cover metal wirings and have plated through holes which expose parts of the respective metal wirings, oxide semiconductor films that electrically conducted with the metal wirings via the plated through holes formed on the insulation films, and an electrical component that includes electrodes which are electrically connected to the oxide semiconductor films. The oxide semiconductor film includes first and second portions in which the widths thereof are different from each other. The width of the first portion is wider than the width of the second portion. A portion faces a part of the metal wiring which is exposed from the plated through hole, and the portion is electrically connected to the part of the metal wiring. At least a part of the second portion faces the electrode of the electrical component and is electrically connected to the electrode.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 4, 2012
    Inventors: Kentaro AGATA, Syou YANAGISAWA, Megumi OOMORI
  • Publication number: 20120228610
    Abstract: A display panel includes a plurality of pads configured to provide a driver thereon, a plurality of first contacts respectively connected to the plurality of pads, a plurality of second contacts respectively provided so as to be opposed to the plurality of first contacts, a polysilicon layer configured to form a plurality of polysilicon films that are respectively extended to connect the plurality of first contacts and the plurality of second contacts to each other, and a gate metal layer different from the polysilicon layer. Each of a plurality of transistors is formed at a position where the to gate metal layer traverses the polysilicon layer, and a plurality of transistor groups are arranged in a zigzag pattern. Each of the plurality of transistor groups include three adjacent transistors of the plurality of transistors.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Inventor: Syou Yanagisawa
  • Patent number: 8188481
    Abstract: A display panel includes a plurality of pads, a plurality of first contacts connected to the pads, a plurality of second contacts provided so as to be opposed to the plurality of first contacts, a polysilicon layer configured to form a plurality of polysilicon films to connect the plurality of first contacts and second contacts, and a gate metal layer. The gate metal layer forms at least one gate metal. The gate metal layer traverses the plurality of polysilicon films so as to form a plurality of transistors. The plurality of transistors are arranged in a zigzag pattern for each transistor set. A width of a portion of each of the polysilicon films, the portion forming a corresponding one of the transistors, is larger than a width of another portion of the polysilicon films. The other portion is connected to a corresponding one of the first contacts and second contacts.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: May 29, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Syou Yanagisawa
  • Patent number: 7924390
    Abstract: A terminal includes a first part, which includes a terminal contact hole and an ITO film, and a second part, which includes the ITO film but not the contact hole. A terminal wiring line of the terminal is wide in the first part and narrow in the second part. In regions adjacent to the first part, adjacent terminal wiring lines are bent outward, thus securing enough interval between wiring lines, with the result that terminals can be formed through patterning by normal light exposure.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: April 12, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Syou Yanagisawa, Nobuyuki Ishige
  • Publication number: 20110079789
    Abstract: A display panel includes a plurality of pads, a plurality of first contacts connected to the pads, a plurality of second contacts provided so as to be opposed to the plurality of first contacts, a polysilicon layer configured to form a plurality of polysilicon films to connect the plurality of first contacts and second contacts, and a gate metal layer. The gate metal layer forms at least one gate metal. The gate metal layer traverses the plurality of polysilicon films so as to form a plurality of transistors. The plurality of transistors are arranged in a zigzag pattern for each transistor set. A width of a portion of each of the polysilicon films, the portion forming a corresponding one of the transistors, is larger than a width of another portion of the polysilicon films. The other portion is connected to a corresponding one of the first contacts and second contacts.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 7, 2011
    Inventor: Syou YANAGISAWA
  • Publication number: 20100321624
    Abstract: First terminals and second terminals, which are terminals of adjacent terminal wires, are staggered in the direction in which wires run, and transparent conductive films provided to the first terminals and second terminals extend so as to overlap the terminal wires outside the regions in which contact holes are created and are formed so as to have a width narrower than the width of the terminal wires in the regions where contact holes are created.
    Type: Application
    Filed: June 16, 2010
    Publication date: December 23, 2010
    Inventor: Syou Yanagisawa
  • Publication number: 20090153008
    Abstract: A terminal includes a first part, which includes a terminal contact hole and an ITO film, and a second part, which includes the ITO film but not the contact hole. A terminal wiring line of the terminal is wide in the first part and narrow in the second part. In regions adjacent to the first part, adjacent terminal wiring lines are bent outward, thus securing enough interval between wiring lines, with the result that terminals can be formed through patterning by normal light exposure.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 18, 2009
    Inventors: Syou Yanagisawa, Nobuyuki Ishige