Abstract: A data processor utilizing a main memory which has a first region for storing a first type of software instruction group for realizing an architecture to prescribe operations of the data processor and a second region for storing a second type of software instruction group which is systematized separately from the first type of software instruction group. A plurality of first registers are defined by a software instruction belonging to the first type of software instruction group. Also provided are a plurality of second registers which are defined by a software instruction belonging to the second type of software instruction group. Further, executing circuitry is provided for executing software instructions belonging to the first type of software instruction group from the main memory in accordance with an instruction program consisting of the second type of software instruction group.

Abstract: An instruction prefetching device of a data processing system prefetches an instruction sequence, usually before decoding of a branch instruction being prefetched, by predicting a branch destination address which is preliminarily stored in a branch history table (46) and retrieved by an instruction address of the branch instruction. Preferably, a prediction evaluating circuit (66) evaluates the predicted destination address with attention directed to a result which is obtained by actually executing the branch instruction and indicates whether the branch instruction indicates "no go" or "go" to the branch. When the prediction is incorrect, the prefetch is suspended. Furthermore, the branch destination address is renewed to a new address obtained by decoding of the branch instruction. More preferably, a discriminator (73) discriminates whether or not the instruction being prefetched is really a branch instruction. If not, the predicted destination address is neglected.