Abstract: A small-size magnetic sensor comprises three axial sensors each configured using plural giant magnetoresistive elements, wherein an X-axis sensor and a Y-axis sensor are arranged on the planar surface of an embedded layer of a substrate, and giant magnetoresistive elements forming a Z-axis sensor are formed on slopes of projections, which are formed by etching the embedded layer. It is possible to form an elongated projection on a substrate by way of the high-density plasma CVD method or by way of plasma etching and microwave etching, so that giant magnetoresistive elements are formed on the slopes of the elongated projection.

Abstract: On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity ions by using as a mask the lamination, side spacer and resist layer. After the resist layer and side spacer are removed, a field oxide film is formed through selective oxidation using the lamination as a mask, and a channel stopper region corresponding to the ion doped region is formed. After the lamination is removed, a circuit device such as a MOS type transistor is formed in each device opening of the field oxide film.

Abstract: A poly-silicon layer is deposited on a surface of a substrate after forming a gate insulating film in an element hole of a field insulating film 12, and thereon a silicon oxide layer is formed by a thermal oxidation process. After patterning the silicon oxide layer in accordance with a gate electrode pattern, the poly-silicon layer is patterned by dry-etching using a remaining resist layer as a mask. After removing the resist layer, a gate electrode layer 16a is formed by decreasing a width of the poly-silicon layer by isotropic etching using the silicon oxide layer 18A as a mask. N+-type source and drain regions 22 and 24 and n?-type source and drain regions 26 and 28 are formed by doping impurity ions via the gate insulating film 14 through the silicon oxide layer 18A. The silicon oxide layer 18A may be made of a layer of tungsten silicide.

Abstract: After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist layer 16 as a mask via the oxidation film 14a. When the oxidation films 14a and 14b are used as sacrificing oxidation films, gate oxidation films are formed in the element holes 12a and 12b after removing the resist film 16 and the oxidation films 14a and 14b. When the oxidation films 14a and 14b are used as gate oxidation films, the oxidation films are once thinned by etching and then thickened after removing the resist layer 16. The gate oxidation film 14a is thicker than the gate oxidation film 14b by forming the ion implantation layer 18.

Abstract: After a field insulating film having an element opening is formed on the surface of a p-type well, a gate insulating film is formed on a semiconductor surface in the element opening. A gate electrode layer of polysilicon or the like is formed on the insulating film. By using as a mask a lamination of the electrode layer and gate insulating film and the field insulating film, an ion implantation process is executed to form n+-type source and drain regions. After the electrode layer is made narrow and thin by an isotropic etching process, n?-type source and drain regions are formed by an ion implantation process using as a mask the lamination of the electrode layer and gate insulating film and the field insulating film.

Abstract: On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity ions by using as a mask the lamination, side spacer and resist layer. After the resist layer and side spacer are removed, a field oxide film is formed through selective oxidation using the lamination as a mask, and a channel stopper region corresponding to the ion doped region is formed. After the lamination is removed, a circuit device such as a MOS type transistor is formed in each device opening of the field oxide film.

Abstract: A poly-silicon layer is deposited on a surface of a substrate after forming a gate insulating film in an element hole of a field insulating film 12, and thereon a silicon oxide layer is formed by a thermal oxidation process. After patterning the silicon oxide layer in accordance with a gate electrode pattern, the poly-silicon layer is patterned by dry-etching using a remaining resist layer as a mask. After removing the resist layer, a gate electrode layer 16a is formed by decreasing a width of the poly-silicon layer by isotropic etching using the silicon oxide layer 18A as a mask. N+-type source and drain regions 22 and 24 and n?-type source and drain regions 26 and 28 are formed by doping impurity ions via the gate insulating film 14 through the silicon oxide layer 18A. The silicon oxide layer 18A may be made of a layer of tungsten silicide.

Abstract: On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity ions by using as a mask the lamination, side spacer and resist layer. After the resist layer and side spacer are removed, a field oxide film is formed through selective oxidation using the lamination as a mask, and a channel stopper region corresponding to the ion doped region is formed. After the lamination is removed, a circuit device such as a MOS type transistor is formed in each device opening of the field oxide film.

Abstract: A small-size magnetic sensor comprises three axial sensors each configured using plural giant magnetoresistive elements, wherein an X-axis sensor and a Y-axis sensor are arranged on the planar surface of an embedded layer of a substrate, and giant magnetoresistive elements forming a Z-axis sensor are formed on slopes of projections, which are formed by etching the embedded layer. It is possible to form an elongated projection on a substrate by way of the high-density plasma CVD method or by way of plasma etching and microwave etching, so that giant magnetoresistive elements are formed on the slopes of the elongated projection.

Abstract: After a field insulating film having an element opening is formed on the surface of a p-type well, a gate insulating film is formed on a semiconductor surface in the element opening. A gate electrode layer of polysilicon or the like is formed on the insulating film. By using as a mask a lamination of the electrode layer and gate insulating film and the field insulating film, an ion implantation process is executed to form n+-type source and drain regions. After the electrode layer is made narrow and thin by an isotropic etching process, n?-type source and drain regions are formed by an ion implantation process using as a mask the lamination of the electrode layer and gate insulating film and the field insulating film.

Abstract: After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist layer 16 as a mask via the oxidation film 14a. When the oxidation films 14a and 14b are used as sacrificing oxidation films, gate oxidation films are formed in the element holes 12a and 12b after removing the resist film 16 and the oxidation films 14a and 14b. When the oxidation films 14a and 14b are used as gate oxidation films, the oxidation films are once thinned by etching and then thickened after removing the resist layer 16. The gate oxidation film 14a is thicker than the gate oxidation film 14b by forming the ion implantation layer 18.