Patents by Inventor Tadaaki Tanimoto
Tadaaki Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012617Abstract: Random number testing is disclosed. In one example, a random number tester includes a register unit that stores a pseudorandom number sequence generated by a random number generator, a next-bit prediction unit that performs machine learning in a learning mode so as to receive a bit string of m bits in the pseudorandom number sequence stored in the register unit as an input, and, according to a predetermined machine learning algorithm, output a desired bit string including a predicted next bit, and a matching probability determination unit that makes, in a test mode, a pass/fail determination on a random number test on the basis of a matching probability based on a next bit following an m-bit bit string in a pseudorandom number sequence generated by the random number generator and of a predicted next bit output from a trained next-bit prediction unit.Type: ApplicationFiled: November 11, 2021Publication date: January 11, 2024Inventor: Tadaaki Tanimoto
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Patent number: 11290257Abstract: To securely realize updating of a key shared between an apparatus on a transmission side and an apparatus on a reception side. A second apparatus encrypts a new shared key by an encryption processing unit, issues a signature for the encrypted new shared key from a signature processing unit, and transmits the signature and the encrypted new shared key to a first apparatus. When a signature processing unit fails in verifying the signature, the first apparatus performs control to prohibit at least one of processing executed after reception of the encrypted new shared key and required to store the new shared key into a storage unit.Type: GrantFiled: April 10, 2019Date of Patent: March 29, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadaaki Tanimoto, Daisuke Moriyama
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Patent number: 10997105Abstract: In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.Type: GrantFiled: April 20, 2020Date of Patent: May 4, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshitaka Taki, Tadaaki Tanimoto
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Patent number: 10949527Abstract: Provided is a semiconductor device which can perform secure data transmission/reception considering functional safety. The semiconductor device includes a hardware security module circuit which performs an authentication process and an error detection circuit used to perform an error detection process at least on first data which is processed in the hardware security module circuit. A memory area associated with the error detection circuit is configured to be accessible only by the hardware security module circuit when the error detection process is performed at least on the first data.Type: GrantFiled: September 20, 2018Date of Patent: March 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadaaki Tanimoto, Daisuke Moriyama, Yoshitaka Taki
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Publication number: 20200394147Abstract: In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.Type: ApplicationFiled: April 20, 2020Publication date: December 17, 2020Inventors: Yoshitaka TAKI, Tadaaki TANIMOTO
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Patent number: 10642596Abstract: An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.Type: GrantFiled: February 28, 2017Date of Patent: May 5, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadaaki Tanimoto, Kesami Hagiwara, Naoyuki Morita
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Patent number: 10642607Abstract: A determination apparatus includes a difference code generation section that generates a first difference code and a second difference code, the first difference code representing a set of code pieces in a first program that are different from code pieces in a second program, the second difference code representing a set of code pieces in the second program that are different from code pieces in the first program, a logical expression derivation section that performs predetermined conversion to derive a first logical expression from the first difference code and derive a second logical expression from the second difference code, and a determination section that, depending on whether the second logical expression includes the first logical expression, determines whether the first program in a predetermined embedded device is dynamically updatable to the second program.Type: GrantFiled: July 21, 2017Date of Patent: May 5, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadaaki Tanimoto, Naoyuki Morita
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Publication number: 20200005183Abstract: Provided are a device, a method, and a program which allow learning models to be appropriately evaluated or trained. The evaluation device according to an aspect performs the steps of: (A) obtaining, using checking data, a first execution result based on a first learning model as an exemplar model; (B) obtaining, using the checking data, a second execution result based on a second learning model; (C) determining whether or not the first and second execution results satisfy a logical formula; and (D) comparing, using a Bayesian statistical model checking method, respective behaviors of the first and second learning models with each other on the basis of a result of the determination in the step (C).Type: ApplicationFiled: June 20, 2019Publication date: January 2, 2020Inventors: Tadaaki TANIMOTO, Motoki KIMURA
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Publication number: 20190342081Abstract: To securely realize updating of a key shared between an apparatus on a transmission side and an apparatus on a reception side. A second apparatus encrypts a new shared key by an encryption processing unit, issues a signature for the encrypted new shared key from a signature processing unit, and transmits the signature and the encrypted new shared key to a first apparatus. When a signature processing unit fails in verifying the signature, the first apparatus performs control to prohibit at least one of processing executed after reception of the encrypted new shared key and required to store the new shared key into a storage unit.Type: ApplicationFiled: April 10, 2019Publication date: November 7, 2019Inventors: Tadaaki TANIMOTO, Daisuke MORIYAMA
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Publication number: 20190156018Abstract: Provided is a semiconductor device which can perform secure data transmission/reception considering functional safety. The semiconductor device includes a hardware security module circuit which performs an authentication process and an error detection circuit used to perform an error detection process at least on first data which is processed in the hardware security module circuit. A memory area associated with the error detection circuit is configured to be accessible only by the hardware security module circuit when the error detection process is performed at least on the first data.Type: ApplicationFiled: September 20, 2018Publication date: May 23, 2019Inventors: Tadaaki TANIMOTO, Daisuke MORIYAMA, Yoshitaka TAKI
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Patent number: 10284553Abstract: In a communication system in which a relay apparatus, a terminal apparatus, and other apparatuses, which can communicate with an authentication apparatus, are coupled through a communication path, the relay apparatus, and the terminal apparatus have unique authentication information, respectively. The relay apparatus transmits its own authentication information and authentication information collected from the terminal apparatus to the authentication apparatus. The authentication apparatus determines whether the relay apparatus and the terminal apparatus are authentic apparatuses based on the received authentication information. The relay apparatus shuts down communication between itself and an apparatus determined to be unauthentic based on a result of the determination, and transmits communication control information to shut down communication with the apparatus determined to be unauthentic to the terminal apparatus.Type: GrantFiled: December 30, 2015Date of Patent: May 7, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoyuki Morita, Tadaaki Tanimoto
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Publication number: 20180337923Abstract: In an authentication method according to an embodiment, a server generates first authentication information configured by a value generated by using a pseudo ransom function using an identifier of an authentication target device and a common key as arguments and transmits the first authentication information to the authentication target device via an authentication proxy client.Type: ApplicationFiled: April 3, 2018Publication date: November 22, 2018Applicant: Renesas Electronics CorporationInventors: Tadaaki TANIMOTO, Daisuke MORIYAMA
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Publication number: 20180088936Abstract: A determination apparatus includes a difference code generation section that generates a first difference code and a second difference code, the first difference code representing a set of code pieces in a first program that are different from code pieces in a second program, the second difference code representing a set of code pieces in the second program that are different from code pieces in the first program, a logical expression derivation section that performs predetermined conversion to derive a first logical expression from the first difference code and derive a second logical expression from the second difference code, and a determination section that, depending on whether the second logical expression includes the first logical expression, determines whether the first program in a predetermined embedded device is dynamically updatable to the second program.Type: ApplicationFiled: July 21, 2017Publication date: March 29, 2018Inventors: Tadaaki TANIMOTO, Naoyuki MORITA
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Publication number: 20170255459Abstract: An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.Type: ApplicationFiled: February 28, 2017Publication date: September 7, 2017Inventors: Tadaaki TANIMOTO, Kesami HAGIWARA, Naoyuki MORITA
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Publication number: 20160219051Abstract: In a communication system in which a relay apparatus, a terminal apparatus, and other apparatuses, which can communicate with an authentication apparatus, are coupled through a communication path, the relay apparatus, and the terminal apparatus have unique authentication information, respectively. The relay apparatus transmits its own authentication information and authentication information collected from the terminal apparatus to the authentication apparatus. The authentication apparatus determines whether the relay apparatus and the terminal apparatus are authentic apparatuses based on the received authentication information. The relay apparatus shuts down communication between itself and an apparatus determined to be unauthentic based on a result of the determination, and transmits communication control information to shut down communication with the apparatus determined to be unauthentic to the terminal apparatus.Type: ApplicationFiled: December 30, 2015Publication date: July 28, 2016Inventors: Naoyuki MORITA, Tadaaki TANIMOTO
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Patent number: 9293022Abstract: The present invention provides a detecting apparatus for detecting an abnormal state such as a drop or fall of a person to be observed from a captured image in a real-time manner and realizing improvement in precision of the detection while eliminating the influence of a background image and noise. The detecting apparatus calculates a motion vector of each of blocks of an image of video data, and extracts a block group in which the size of the motion vector exceeds a predetermined value. The detecting apparatus forms a group from adjacent blocks. For example, in descending order of the area of the blocks, the detecting apparatus calculates characteristic amounts such as an average vector, a variance, and a rotation direction component of motion blocks included in the blocks. The detecting apparatus detects that the person to be observed is in an abnormal state such as a drop or fall on the basis of the characteristic amounts of the groups, and informs an external apparatus or the like of the detection result.Type: GrantFiled: October 29, 2014Date of Patent: March 22, 2016Assignee: Renesas Electronics CorporationInventors: Takayuki Kurosawa, Tadaaki Tanimoto
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Publication number: 20150139504Abstract: The present invention provides a detecting apparatus for detecting an abnormal state such as a drop or fall of a person to be observed from a captured image in a real-time manner and realizing improvement in precision of the detection while eliminating the influence of a background image and noise. The detecting apparatus calculates a motion vector of each of blocks of an image of video data, and extracts a block group in which the size of the motion vector exceeds a predetermined value. The detecting apparatus forms a group from adjacent blocks. For example, in descending order of the area of the blocks, the detecting apparatus calculates characteristic amounts such as an average vector, a variance, and a rotation direction component of motion blocks included in the blocks. The detecting apparatus detects that the person to be observed is in an abnormal state such as a drop or fall on the basis of the characteristic amounts of the groups, and informs an external apparatus or the like of the detection result.Type: ApplicationFiled: October 29, 2014Publication date: May 21, 2015Applicant: Renesas Electronics CorporationInventors: Takayuki KUROSAWA, Tadaaki TANIMOTO
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Patent number: 8799838Abstract: Specific characteristics of a branch structure between a behavioral description and a hardware description, a structural dependence relation therebetween, and the like are extracted and used to shorten the time of processing for equivalence checking, thereby contributing to the shortening of a processing time required for equivalence checking for a high-level description and a behavioral synthesis result. Upon checking of the equivalence of a high-level description and a synthesis result obtained by performing a behavior synthesis on the high-level description according to a behavioral synthesis restriction, correspondence information between flip-flops with a feedback loop in the synthesis result and variables associated therewith with a backward data dependence relation in a high-level description is generated and used.Type: GrantFiled: February 19, 2013Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Tadaaki Tanimoto, Shintaro Imamura
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Patent number: 8719744Abstract: A language conversion method includes a first process in which a computer unit inputs algorithm description data describing an algorithm of hardware under a predetermined description constraint using a program description language, a second process in which the computer unit inputs hardware element specification data specifying parameters representing hardware elements included in the algorithm description data, and a third process in which the computer unit converts the algorithm description data into data of a hardware model based on a system level description language, wherein, in the third process, the computer unit generates a data dependency preservation description which preserves, in the hardware model, data dependency in the algorithm description with regard to a parameter specified in the hardware element specification data.Type: GrantFiled: June 8, 2012Date of Patent: May 6, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiki Oshima, Tadaaki Tanimoto
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Publication number: 20130014091Abstract: A language conversion method includes a first process in which a computer unit inputs algorithm description data describing an algorithm of hardware under a predetermined description constraint using a program description language, a second process in which the computer unit inputs hardware element specification data specifying parameters representing hardware elements included in the algorithm description data, and a third process in which the computer unit converts the algorithm description data into data of a hardware model based on a system level description language, wherein, in the third process, the computer unit generates a data dependency preservation description which preserves, in the hardware model, data dependency in the algorithm description with regard to a parameter specified in the hardware element specification data.Type: ApplicationFiled: June 8, 2012Publication date: January 10, 2013Applicant: Renesas Electronics CorporationInventors: Yoshiki Oshima, Tadaaki Tanimoto