Patents by Inventor Tadahide Hoshi

Tadahide Hoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5951755
    Abstract: A manufacturing method for manufacturing a semiconductor substrate has first annealing step for annealing silicon single crystal to permit oxygen embryos or oxygen precipitations grown from the oxygen embryos precipitating in a predetermined region and a second annealing step for permitting said oxygen embryos or said oxygen precipitations to contract using a second temperature range higher than the first temperature range, said second temperature range being high enough to contract said oxygen embryos and low enough to prevent redistribution of boron from affecting to device characteristics, to form a denuded zone in said predetermined region at the principal surface. An inspection method for inspecting a semiconductor substrate further has measuring step, subsequent to said first and second annealing steps for measuring the density of oxygen embryos grown into oxygen precipitations among those precipitated in said silicon single crystal.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: September 14, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Masanobu Ogino, Tadahide Hoshi, Masanori Numano, Shuichi Samata, Akiko Sekihara, Keiko Akita
  • Patent number: 5352625
    Abstract: In manufacturing a semiconductor substrate having a dielectric isolation structure, a dielectric film is formed at a semiconductor layer formed by epitaxial growth. Grooves for carrying out dielectric isolation to deposit filler thereon thereafter are used to polish the deposited filler. The polishing condition is obeyed where polishing rate ratio of the filler to the dielectric film is one fifth or less. Thus, an active semiconductor layer in which where elements are to be formed can be provided with good productivity, state where the flatness thereof is good and the layer thickness is uniformly and precisely controlled.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: October 4, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahide Hoshi
  • Patent number: 5273553
    Abstract: There is provided a method for bonding at least two semiconductor wafers to each other which comprises the steps of warping one of the semiconductor wafers, bringing the warped semiconductor wafer into contact with the other semiconductor wafer at one contact point, and reducing pressure in an atmosphere surrounding the semiconductor wafers to flatten the warped semiconductor wafer. An apparatus for bonding wafers using the above bonding method comprises a first wafer holder for warping and holding one of two wafers and a second wafer holder for holding the other wafer. First and second covers are attached so as to surround the first and second wafer holders. The apparatus further comprises a shaft for rotating the first and second wafer holders so that one of the wafers contact the other wafer at one contact point and the first and second covers are connected to each other to form a chamber.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: December 28, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahide Hoshi, Kiyoshi Yoshikawa
  • Patent number: 5196375
    Abstract: A method for manufacturing a bonded semiconductor body including contacting the flat mirror surfaces of semiconductor substrate wafers used as semiconductor element substrates, and subjecting the adhered semiconductor substrate wafers to a heat treatment at a temperature higher than 200.degree. C. and lower than the melting point of the semiconductor substrate wafers to bond the mirror surfaces. The surface roughness of each of the mirror surfaces of the semiconductor substrate wafers is set not more than 130 .ANG. at its maximum value when measured in a range of 1 mm on a reference plane provided in a predetermined area of the mirror surface.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: March 23, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahide Hoshi
  • Patent number: 5129827
    Abstract: There is provided a method for bonding at least two semiconductor wafers to each other which comprises the steps of warping one of the semiconductor wafers, bringing the warped semiconductor wafer into contact with the other semiconductor wafer at one contact point, and reducing pressure in an atmosphere surrounding the semiconductor wafers to flatten the warped semiconductor wafer. An apparatus for bonding wafers using the above bonding method comprises a first wafer holder for warping and holding one of two wafers and a second wafer holder for holding the other wafer. First and second covers are attached so as to surround the first and second wafer holders. The apparatus further comprises a shaft for rotating the first and second wafer holders so that one of the wafers contact the other wafer at one contact point and the first and second covers are connected to each other to form a chamber.
    Type: Grant
    Filed: August 24, 1990
    Date of Patent: July 14, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahide Hoshi, Kiyoshi Yoshikawa
  • Patent number: 5068704
    Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semiconductor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.
    Type: Grant
    Filed: May 8, 1990
    Date of Patent: November 26, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kaoru Imamura, Ryo Sato, Tadahide Hoshi
  • Patent number: 4935386
    Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semicondutor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.
    Type: Grant
    Filed: February 26, 1988
    Date of Patent: June 19, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kaoru Imamura, Ryo Sato, Tadahide Hoshi