Abstract: Provided is a test apparatus for testing a device under test, including a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals, a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe, and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

Abstract: A signal measuring apparatus that measures a first input signal and a second input signal is provided, including a first measuring section that measures the first input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a second measuring section that measures the second input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a phase difference calculating section that calculates phase differences between the first input signal and the second input signal in each measurement cycle based on measurement results from the first measuring section and the second measuring section, and a distribution generating section that generates distribution information of the phase differences calculated in each measurement cycle by the phase difference calculating section.

Abstract: Provided is a test apparatus for testing a device under test, comprising a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals; a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe; and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

Abstract: A signal measuring apparatus that measures a first input signal and a second input signal is provided, including a first measuring section that measures the first input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a second measuring section that measures the second input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a phase difference calculating section that calculates phase differences between the first input signal and the second input signal in each measurement cycle based on measurement results from the first measuring section and the second measuring section, and a distribution generating section that generates distribution information of the phase differences calculated in each measurement cycle by the phase difference calculating section.

Abstract: A changing point detection circuit is provided that detects timing of changing points at which a logic value of a signal under measurement changes and includes a multi-strobe circuit generating a logic value data string obtained by detecting a logic value of the signal under measurement according to a plurality of strobes, each strobe having a different phase; a changing point detecting section detecting in which strobe the logic value changes based on the logic value data string; an edge designation storage section storing in advance information concerning whether an edge-type of the changing point to be detected is a rising edge or a falling edge of the signal under measurement; a selecting section selecting the changing point corresponding to the edge-type stored by the edge designation storage section from among the changing points detected by the changing point detecting section; and a strobe place storage section storing information concerning which strobe the changing point selected by the selecting se

Abstract: There is disclosed a semiconductor test apparatus enabling writing into an information write space of a block including a failure cell into which block writing is inhibited partially or entirely by the bad block mask function and the fail loop back function. A pattern generation block outputs to an output controller a release signal (S4) for releasing the write inhibit instruction defined by an inhibit signal (S3) and a mask signal (SI). When the output controller receives the release signal (S4), the output controller outputs a write enable signal (WE) to an MUT (4).

Abstract: There is disclosed a semiconductor test apparatus enabling writing into an information write space of a block including a failure cell into which block writing is inhibited partially or entirely by the bad block mask function and the fail loop back function. A pattern generation block outputs to an output controller a release signal (S4) for releasing the write inhibit instruction defined by an inhibit signal (S3) and a mask signal (SI). When the output controller receives the release signal (S4), the output controller outputs a write enable signal (WE) to an MUT (4).

Abstract: A test data pattern, an address pattern, and a control signal are supplied from a pattern generator to a test memory. Data read from the test memory is compared with expected data by an XOR gate. When they match, a compared result that represents pass is output. When they mismatch, a compared result that represents fail is output. A match signal WC detected by the XOR gate is held in a register. The register outputs an inhibition signal to an inhibition gate of the test memory. Thus, a write enable signal WE is inhibited from being supplied to the test memory. In addition, the inhibition signal is supplied to a compared result inhibition gate. The compared result inhibition gate causes the compared result to be passed and prevents the test memory from being excessively written.