Abstract: A neural network apparatus and method for use in applications such as in a voltage/reactive-power controller in which a neuro control-object simulator and a neuro controller pre-learn so as to make input-output relations of the controller match the input-output relations of a control unit and so as to make input-output relations of the simulator match input-output relations of a control object. The controller re-learns so as to make the output of the simulator match an input corresponding to a desired output of the control object. After re-learning, the controller controls the control-object.

Abstract: A digital data processing system in which system parameters in an electric power system such as current or voltage are sampled at predetermined time intervals and converted into digital data by analog-to-digital converter units. The sampling frequency is made higher than the expected frequency of variation of these parameters. Sensing units located remotely from one another sample these parameters at rates which are asynchronous between sensing units. The data transmitted from the various sensing units is sent to a central processing unit where the received signals are sampled synchronously and then processed in order to provide protection for the electric power system.

Abstract: At each of terminal connected to a protected line section a current is sampled at an identical high sampling frequency, digitized, encoded and transmitted to an associated one of the terminals with the digitized data registered in a first buffer memory. Those processes are conducted under the control of respective clock pulses. Also a receiver receives similar data from the associated terminal. The received data are decoded and registered in a second buffer memory under the control of control signals from the receiver. A shift register successively receives the data from the first buffer memory and shifts them through it under the control of a shifting pulse to compensate for a known transmission delay between the data in the two buffer memories. The shift register and the second buffer memory write respective data into a processing unit in response to a writing pulse having a pulse width of a sampling pulse multiplied by an integer from the processing unit.