Patents by Inventor Tadahiro Kato

Tadahiro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6239039
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 29, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6220928
    Abstract: The present invention provides a surface grinding method and apparatus for achieving a thin plate work such as a semiconductor wafer with high flatness, high accuracy and certainty and the apparatus comprises: a surface grinder in which a grinding wheel support member 3 by which a rotary shaft 5 of a grinding wheel 6 is supported is held by a pivotal shaft portion 4 and a grinding wheel shaft inclination control motor 9 which displaces the grinding wheel support member 3 by activating the pivotal shaft portion 4 is provided; a corrective angle storage device 15 which stores a corrective angle of an inclination angle of a rotary shaft 5 of the grinding wheel 6 to a rotary shaft 13 of a wafer 12; and a shaft inclination control apparatus 14 which sends out a signal to control the grinding wheel shaft inclination control motor 9 while reading a corrective angle of the corrective angle storage device 15, wherein a relative inclination angle of the grinding wheel to the thin plate work, in a more concrete manner a
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: April 24, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Keiichi Okabe, Hisashi Oshima, Sadayuki Okuni, Tadahiro Kato
  • Patent number: 6077149
    Abstract: In a surface-grinding method for a workpiece, for example a semiconductor wafer, it is possible to correct or improve waviness and bow and to obtain a semiconductor wafer having no thickness dispersion. Besides, wafer processing to higher precision than that conventionally attained is achieved and at the same time simplification of the processing method and thereby reduction of the cost are also achieved. In the present invention, while the workpiece is fixed for supporting at one surface by the fixedly supporting means of a surface-grinding apparatus, the other surface of the workpiece is surface-ground, where the workpiece adheres on the upper surface of a base plate by the aid of adhesive material and the base plate is fixedly supported by the lower surface of itself on the fixedly supporting means.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: June 20, 2000
    Assignee: Shin-etsu Handotai Co., Ltd.
    Inventors: Sadayuki Ohkuni, Tadahiro Kato, Hideo Kudo
  • Patent number: 6050880
    Abstract: A surface grinding method for a thin-plate workpiece is provided including the steps of (a) roughly surface grinding a first surface of a thin-plate workpiece using a thin-plate workpiece surface grinding device to create a reference plane having no sori or waviness; (b) inverting the thin-plate workpiece, the first surface of which has been roughly surface ground and, with a surface grinding device having a hard chucking plate, chucking the first surface to the hard chucking plate to roughly surface grind a second surface of the thin-plate workpiece; (c) chucking to the hard chucking plate the first surface of the thin-plate workpiece, the second surface of which has been roughly surface ground with the surface grinding device having the hard chucking plate to further finely surface grind the second surface of the thin-plate workpiece; and (d) inverting the thin-plate workpiece, the second surface of which has been finely surface ground and, with the surface grinding device having the hard chucking plate, ch
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: April 18, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Sadayuki Okuni, Hideo Kudo, Hiroshi Tomioka
  • Patent number: 5951374
    Abstract: A method of polishing semiconductor wafers includes a double side primary polishing step and a single side secondary polishing step using a single side polishing machine with a wafer holder including a template so bonded on a carrier plate as having one or more wafer receiving holes in which backing pads are disposed respectively for holding the back sides of the respective wafers fittingly received therein. This method makes it to possible to hold a plurality of wafers at one time due to batch processing to thereby improve the productivity, and decrease extremely the generation of the defective dimples in the front side of the wafer. Compared with conventional single side polishing, the flatness level of the wafer polished with the double side polishing machine in this method is improved.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 14, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Masumura, Masami Nakano, Hideo Kudo
  • Patent number: 5942445
    Abstract: According to the invention, the flatness and quality can be improved while simplifying the process even when large size wafers of 200 to 300 mm or above are processed. Basic steps involved are a slicing step E for obtaining thin disc-shape wafers by slicing, a chamfering step F for chamfering the sliced wafers, a flattening step G for flattening the chamfered wafers, an alkali etching step H for removing process damage layers from the flattened wafers, and a double-side polishing step K of simultaneously polishing the two sides of the etched wafers. If necessary, a plasma etching step is used in lieu of the flattening and etching steps G and H respectively.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: August 24, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Masumura, Sadayuki Okuni, Hideo Kudo
  • Patent number: 5800725
    Abstract: A method of manufacturing semiconductor wafers includes a double side primary polishing step, a back side etching step and a single side mirror polishing step. This method is capable of easy sensor detection of the front and back sides of the wafer, wafer processing of higher flatness level by forming etched rough surface at the back side of the double side polished wafer and setting up of wafer manufacturing process including a double side polishing step.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 1, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Masumura, Hideo Kudo
  • Patent number: 5679212
    Abstract: The work of grinding of a silicon wafer is carried out in an etchant containing no loose abrasive and permitting selective etching of deformed layers existent in the surface part of said wafer. The removal of the deformed layers and the heavy metals from the wafer is effected simultaneously and quickly owing to the execution of the work of grinding in the etchant and the consequent synergism of the work of grinding and etching.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: October 21, 1997
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hideo Kudo
  • Patent number: 5494862
    Abstract: A method for a flatter semiconductor wafer free of ORP-observed irregularity and particles generated in handling on the back side of the wafer, in which an alkaline etching is adopted to utilize its advantage and a slight polishing step is combined to a conventional method of this kind. A deficiency of alkaline etching which brings about rougher surface irregularities on the surface of a wafer is eliminated by the use of the step of slight polishing on the back surface after the etching step and the inherent advantage stands without a loss, so that particle generation from the back surface of a semiconductor wafer in handling is much reduced and what's more a flatter semiconductor wafer is realized and a yield of an electronic device fabrication is increased.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: February 27, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Masami Nakano, Sunao Shima, Hisashi Masumura
  • Patent number: 5474644
    Abstract: A method and an apparatus for high-flatness etching a semiconductor single crystal wafer wherein said wafer is so rotated in a flow of an ethchant radially spreading in a plane that the main surface of said wafer may move parallelly with the flow of said etchant.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: December 12, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hideo Kudo
  • Patent number: 5447890
    Abstract: A wafer which allows manufacture of a device to proceed at an exalted yield by preventing the resolution of exposure at the step of photolithography during the manufacture of the device from being impaired is obtained by a method which comprises a slicing step for slicing a single crystal ingot thereby obtaining wafers of the shape of a thin disc, a chamfering step for chamfering the wafer obtained by the slicing step, a lapping step for imparting a flat surface to the chamfered wafer, an etching step for removing mechanical strain remaining in the lapped wafer, an obverse surface-polishing step for polishing one side of the etched wafer, and a cleaning step for cleaning the polished wafer, which method is characterized by interposing between the etching step and the obverse surface-polishing step a reverse surface-preparing step for preparing the shape of the reverse side of the wafer.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: September 5, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Sunao Shima, Masami Nakano, Hisashi Masumura, Hideo Kudo
  • Patent number: 4759961
    Abstract: In a method for forming coatings, comprising the steps of applying a base coating containing a coloring pigment and/or a metallic pigment to produce a base coat, applying a topcoating containing a hydroxyl group-containing resin and a polyisocyanate compound over the base coat, and curing the coats at a temperature range between room temperature to about 140.degree. C., the method which is characterized in that the base coating contains the following as a vehicle component;(a) a resin having hydroxyl group and carboxyl group in the molecule,(b) a combination of the resin having hydroxyl group in the molecule and a catalyst for promoting the reaction between the hydroxyl group of the resin and the isocyanate group of the polyisocyanate compound in the topcoating or(c) a combination of the resin having hydroxyl group and carboxyl group in the molecule and a catalyst for promoting the reaction between the hydroxyl group of the resin and the isocyanate group of the polyisocyanate compound in the topcoating.
    Type: Grant
    Filed: May 12, 1987
    Date of Patent: July 26, 1988
    Assignee: Kansai Paint Company, Limited
    Inventors: Tadahiro Kato, Yasuhiro Fujii, Hiroaki Kiyata, Masaru Mitsuzi, Mototaka Iihashi