Patents by Inventor Tadahiro Morifuji
Tadahiro Morifuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11037897Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: November 14, 2019Date of Patent: June 15, 2021Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20200098713Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: November 14, 2019Publication date: March 26, 2020Applicant: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 10510700Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: June 26, 2018Date of Patent: December 17, 2019Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20180301429Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: June 26, 2018Publication date: October 18, 2018Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 10032739Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: May 10, 2017Date of Patent: July 24, 2018Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20170243844Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 9685419Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: July 26, 2016Date of Patent: June 20, 2017Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20160336288Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 9466583Abstract: A semiconductor chip includes an electrode pad on a substrate, a barrier metal layer on the electrode pad, a bump electrode, a first protection layer formed on the substrate, and a second protection layer having an opening. The first protection layer overlaps part of the electrode pad. The second protection layer covers a region over the first protection layer and a region over the electrode pad. The upper surface of the second protection layer has an arc surface. The thickness between the arc surface and the electrode pad as seen in a sectional view is gradually large from the rim of the opening to the rim of the electrode pad. The rate of change of the thickness is higher at the rim of the opening than at the rim of the electrode pad.Type: GrantFiled: July 20, 2015Date of Patent: October 11, 2016Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20150325541Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 9123628Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: September 19, 2014Date of Patent: September 1, 2015Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 9053991Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: July 22, 2014Date of Patent: June 9, 2015Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20150021765Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: September 19, 2014Publication date: January 22, 2015Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 8922010Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: April 4, 2013Date of Patent: December 30, 2014Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20140332954Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: July 22, 2014Publication date: November 13, 2014Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 8883566Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.Type: GrantFiled: April 9, 2014Date of Patent: November 11, 2014Assignees: Rohm Co., Ltd., Renesas Electronics CorporationInventors: Tadahiro Morifuji, Haruo Shimamoto, Chuichi Miyazaki, Toshihide Uematsu, Yoshiyuki Abe
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Publication number: 20140220740Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicants: ROHM CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Tadahiro MORIFUJI, Haruo SHIMAMOTO, Chuichi MIYAZAKI, Toshihide UEMATSU, Yoshiyuki ABE
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Patent number: 8729698Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.Type: GrantFiled: August 31, 2010Date of Patent: May 20, 2014Assignees: Rohm Co., Ltd., Renesas Electronics CorporationInventors: Tadahiro Morifuji, Haruo Shimamoto, Chuichi Miyazaki, Toshihide Uematsu, Yoshiyuki Abe
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Patent number: 8653657Abstract: There are provided a semiconductor device capable of accurately determining whether a semiconductor chip is bonded to a solid-state device such as the other semiconductor chip parallelly with each other, a semiconductor chip used for the semiconductor device, and a method of manufacturing the semiconductor chip. The semiconductor chip includes a functional bump projected with a first projection amount from the surface of the semiconductor chip and electrically connecting the semiconductor chip to the solid-state device, and a connection confirmation bump projected with a second projection amount, which is smaller than the first projection amount, from the surface of the semiconductor chip and used for confirming the state of the electrical connection by the functional bump.Type: GrantFiled: August 18, 2006Date of Patent: February 18, 2014Assignee: Rohm Co., Ltd.Inventors: Osamu Miyata, Tadahiro Morifuji
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Publication number: 20130256881Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: April 4, 2013Publication date: October 3, 2013Applicant: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda