Patents by Inventor Tadami Tanaka
Tadami Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7704318Abstract: When growing a silicon single crystal free of grown-in defects based on the CZ method, the crystal is pulled out at a critical pulling rate at which a ring-shaped OSF occurrence region vanishes in a center portion of the crystal by using a hot zone structure in which a temperature gradient Gc in a center portion of the crystal is equal to or greater than a temperature gradient Ge in a peripheral portion of the crystal, while supplying an inert gas including hydrogen to an interior of a pulling furnace. The critical pulling rate at which the ring-shaped OSF occurrence region vanishes in the center portion of the crystal is increased, and single crystals free of grown-in defects in which dislocation clusters and COPs can be grown by pulling at a pulling rate higher than that of the prior art.Type: GrantFiled: February 25, 2004Date of Patent: April 27, 2010Assignee: Sumco CorporationInventors: Masataka Hourai, Wataru Sugimura, Toshiaki Ono, Tadami Tanaka
-
Publication number: 20060156969Abstract: In the present invention, when growing a silicon single crystal free of grown-in defects by the CZ method, the crystal is pulled out at or in a vicinity of a critical pulling rate at which a ring-shaped OSF occurrence region vanishes in a center portion of the crystal by using a hot zone structure in which a temperature gradient Gc in a center portion of the crystal is equal to or greater than a temperature gradient Ge in a peripheral portion of the crystal, while supplying an inert gas including hydrogen to an interior of a pulling furnace. By means of the present invention, the critical pulling rate at which the ring-shaped OSF occurrence region vanishes in the center portion of the crystal is increased, and single crystals free of grown-in defects in which dislocation clusters and COPs do not exist over the entire crystal radial direction in the as-grown state, can be grown by pulling at a pulling rate higher an that in the prior art.Type: ApplicationFiled: February 25, 2004Publication date: July 20, 2006Applicant: SUMCO CORPORATIONInventors: Masataka Hourai, Wataru Sugimura, Toshiaki Ono, Tadami Tanaka
-
Patent number: 7014704Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3–1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.–1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ? of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79). With this method, the silicon single crystal, in which the generation of Grown-in defects can be effectively suppressed, can be produced in a simple process without any increase in the production cost.Type: GrantFiled: June 6, 2003Date of Patent: March 21, 2006Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Tadami Tanaka, Shigeru Umeno, Eiichi Asayama, Hideshi Nishikawa
-
Patent number: 6905771Abstract: A silicon wafer is doped with boron and germanium in a range that satisfies a relational expression defined by: ?0.8×10?3?4.64×10?24×[Ge]?2.69×10?23×[B]?1.5×10?3. This can reduce the miss-fit dislocation which might be induced when an epitaxial layer is grown over the silicon wafer that has been added with boron in high concentration. It is to be noted that in the above relational expression, the [B] denotes a boron concentration, while the [Ge] denotes a germanium concentration and a concentration unit is indicated by atoms/cm3.Type: GrantFiled: November 10, 2003Date of Patent: June 14, 2005Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Tadami Tanaka, Masataka Hourai
-
Patent number: 6835245Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.Type: GrantFiled: June 20, 2001Date of Patent: December 28, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Tadami Tanaka, Eiichi Asayama, Hideshi Nishikawa, Masataka Horai
-
Publication number: 20040244674Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3-1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.-1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ⅗ of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79).Type: ApplicationFiled: June 6, 2003Publication date: December 9, 2004Inventors: Toshiaki Ono, Tadami Tanaka, Shigeru Umeno, Eiichi Asayama, Hideshi Nishikawa
-
Publication number: 20040089225Abstract: A silicon wafer is doped with boron and germanium in a range that satisfies a relational expression defined by: −0.8×10−3≦4.64×10−24×[Ge]−2.69×10−23×[B]≦1.5×10−3. This can reduce the miss-fit dislocation which might be induced when an epitaxial layer is grown over the silicon wafer that has been added with boron in high concentration. It is to be noted that in the above relational expression, the [B] denotes a boron concentration, while the [Ge] denotes a germanium concentration and a concentration unit is indicated by atoms/cm3.Type: ApplicationFiled: November 10, 2003Publication date: May 13, 2004Inventors: Toshiaki Ono, Tadami Tanaka, Masataka Hourai
-
Patent number: 6709957Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 atoms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.Type: GrantFiled: June 18, 2002Date of Patent: March 23, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Eiichi Asayama, Yasuo Koike, Tadami Tanaka, Toshiaki Ono, Masataka Horai, Hideshi Nishikawa
-
Patent number: 6569237Abstract: A method of producing high-quality epitaxial wafers with scarce occurrence of epitaxial layer defects by allowing an epitaxial layer on wafers sliced from a nitrogen-doped silicon single crystal as well as a method of pulling up a silicon single crystal to serve as the raw material therefore is provided. More particularly, a method of pulling up a single crystal from a nitrogen-doped silicon material melt while allowing the single crystal to grow is provided which comprises employing a passing or residence time in the temperature range of 1150-1050° C. of not less than 50 minutes and/or a passing or residence time in the temperature range of 1050-950° C. of not more than 40 minutes in the step of pulling up of the single crystal. Further, a method of manufacturing epitaxial wafers is provided which comprises allowing an epitaxial layer on the surface of silicon wafers sliced from the single crystal pulled up by the method mentioned above.Type: GrantFiled: June 21, 2001Date of Patent: May 27, 2003Assignee: Sumitomo Metal Industries, Ltd.Inventors: Tadami Tanaka, Toshiaki Ono, Eiichi Asayama
-
Patent number: 6514335Abstract: A method of producing a high-quality silicon single crystal of a large diameter and a long size in a good yield by controlling the positions where ring-like oxygen-induced stacking faults (R-OSF) occur in the crystal faces and minimizing grown-in defects such a dislocation clusters and infrared scattering bodies that are introduced in the pulling step. Wafers produced from the above-high-quality silicon single crystal contain little harmful defects that would deteriorate device characteristics and can be effectively adapted to larger scale integration and size reduction of the devices. Therefore, the method can be extensively utilized in the field of producing semiconductor silicon single crystals.Type: GrantFiled: February 24, 2000Date of Patent: February 4, 2003Assignee: Sumitomo Metal Industries, Ltd.Inventors: Kazuyuki Egashira, Masahiko Okui, Manabu Nishimoto, Tadami Tanaka, Shunji Kuragaki, Takayuki Kubo, Shingo Kizaki, Junji Horii, Makoto Ito
-
Publication number: 20030008447Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 at ms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.Type: ApplicationFiled: June 18, 2002Publication date: January 9, 2003Inventors: Eiichi Asayama, Yasuo Koike, Tadami Tanaka, Toshiaki Ono, Masataka Horai, Hideshi Nishikawa
-
Publication number: 20020017234Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.Type: ApplicationFiled: June 20, 2001Publication date: February 14, 2002Applicant: Sumitomo Metal Industries, Ltd., Osaka-shi, JapanInventors: Toshiaki Ono, Tadami Tanaka, Eiichi Asayama, Hideshi Nishikawa, Masataka Horai
-
Publication number: 20020000189Abstract: A method of producing high-quality epitaxial wafers with scarce occurrence of epitaxial layer defects by allowing an epitaxial layer on wafers sliced from a nitrogen-doped silicon single crystal as well as a method of pulling up a silicon single crystal to serve as the raw material therefore is provided. More particularly, a method of pulling up a single crystal from a nitrogen-doped silicon material melt while allowing the single crystal to grow is provided which comprises employing a passing or residence time in the temperature range of 1150-1050° C. of not less than 50 minutes and/or a passing or residence time in the temperature range of 1050-950° C. of not more than 40 minutes in the step of pulling up of the single crystal. Further, a method of manufacturing epitaxial wafers is provided which comprises allowing an epitaxial layer on the surface of silicon wafers sliced from the single crystal pulled up by the method mentioned above.Type: ApplicationFiled: June 21, 2001Publication date: January 3, 2002Applicant: SUMITOMO METAL INDUSTRIES, LTD.Inventors: Tadami Tanaka, Toshiaki Ono, Eiichi Asayama
-
Patent number: 6113687Abstract: A silicon single crystal wafer having good device characteristics can be manufactured according to the Czochralski method without formation of any dislocation cluster within a crystal surface. Where a silicon single crystal having an oxygen concentration of less than 8.5.times.10.sup.17 atoms/cm.sup.3 (ASTM F1188-88) is manufactured, a radius of a latent zone of oxidation induced stacking defects ring-likely-distributed in the crystal surface is made within a range of 70% to 0% of a crystal radius, and a value of V/G (mm.sup.2 /.degree. C..multidot.minute) is controlled at a predetermined critical value or over at radial positions except an outermost periphery of the crystal when a pulling rate is taken as V (mm/minute), and a crystalline temperature gradient along the pulling axis is taken as G (.degree. C./mm). On the other hand, when a silicon single crystal having an oxygen concentration of not less than 8.5.times.10.sup.17 atoms/cm.sup.Type: GrantFiled: November 17, 1998Date of Patent: September 5, 2000Assignee: Sumitomo Metal Industries, Ltd.Inventors: Masataka Horai, Kazuyuki Egashira, Tadami Tanaka