Patents by Inventor Tadao Ishibashi
Tadao Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11217705Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).Type: GrantFiled: June 6, 2019Date of Patent: January 4, 2022Assignee: NTT ELECTRONICS CORPORATIONInventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
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Publication number: 20190312150Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).Type: ApplicationFiled: June 6, 2019Publication date: October 10, 2019Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
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Patent number: 10367100Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).Type: GrantFiled: August 13, 2015Date of Patent: July 30, 2019Assignee: NTT ELECTRONICS CORPORATIONInventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
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Patent number: 9857217Abstract: An opto-electronic integrated circuit includes an optical splitter (12, 13A, 13B) formed on a substrate, the optical splitter branching an input optical signal into N (N is an integer of 2 or more) optical signals, and outputting the optical signals, and N optical phase modulators (15A-15D) formed on the substrate for the respective optical signals output from the optical splitter, the optical phase modulators adjusting the phases of the optical signals based on a phase modulation characteristic in which the phase change amount changes depending on the wavelength of light, and output the optical signals.Type: GrantFiled: September 21, 2012Date of Patent: January 2, 2018Assignees: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, NTT ELECTRONICS CORPORATIONInventors: Atsushi Wakatsuki, Tadao Ishibashi
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Publication number: 20170323981Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).Type: ApplicationFiled: August 13, 2015Publication date: November 9, 2017Inventors: Makoto SHIMIZU, Hiroki ITOH, Tadao ISHIBASHI, Isamu KOTAKA
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Patent number: 9276158Abstract: A photodiode that can provide a THz operation with a stable output. A photodiode having a pin-type semiconductor structure includes a semiconductor layer structure and n and p electrodes. The semiconductor layer structure is obtained by sequentially layering an n-type contact layer, a low concentration layer, and a p-type contact layer. The low concentration layer is obtained by layering an electron drift layer, a light absorption layer, and a hole drift layer while being abutted to the n-type contact layer. The n electrode and the p electrode are connected to the n-type contact layer and the p-type contact layer, respectively. During operation, the low concentration layer is depleted.Type: GrantFiled: October 4, 2013Date of Patent: March 1, 2016Assignee: NTT Electronics CorporationInventors: Tadao Ishibashi, Hiroki Itoh, Makoto Shimizu
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Patent number: 9229179Abstract: An integrated optoelectronic module comprising: a semiconductor substrate; a single-mode optical waveguide comprising a semiconductor with a signal input section at a first end; a multi-mode optical waveguide comprising a semiconductor connected to a second end of the single-mode optical waveguide; and a photodiode disposed on and adjacent to the multi-mode interferometer waveguide and having at least one optical absorption layer section, wherein the single-mode optical waveguide, the multi-mode optical waveguide, and the photodiode being stacked on the semiconductor substrate, wherein the multi-mode interferometer waveguide comprises a reflection section formed by partly grooving the multi-mode interferometer waveguide, and an optical signal having propagated through the multi-mode interferometer waveguide is reflected by the reflection section and focused on the optical absorption layer section.Type: GrantFiled: June 17, 2013Date of Patent: January 5, 2016Assignee: NTT Electronics CorporationInventor: Tadao Ishibashi
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Publication number: 20150287869Abstract: A photodiode that can provide a THz operation with a stable output. A photodiode having a pin-type semiconductor structure includes a semiconductor layer structure and n and p electrodes. The semiconductor layer structure is obtained by sequentially layering an n-type contact layer, a low concentration layer, and a p-type contact layer. The low concentration layer is obtained by layering an electron drift layer, a light absorption layer, and a hole drift layer while being abutted to the n-type contact layer. The n electrode and the p electrode are connected to the n-type contact layer and the p-type contact layer, respectively. During operation, the low concentration layer is depleted.Type: ApplicationFiled: October 4, 2013Publication date: October 8, 2015Applicant: NTT ELECTRONICS CORPORATIONInventors: Tadao Ishibashi, Hiroki Itoh, Makoto Shimizu
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Patent number: 9006854Abstract: An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an outType: GrantFiled: September 1, 2011Date of Patent: April 14, 2015Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone CorporationInventors: Tadao Ishibashi, Seigo Ando, Masahiro Nada, Yoshifumi Muramoto, Haruki Yokoyama
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Publication number: 20140231627Abstract: An opto-electronic integrated circuit includes an optical splitter (12, 13A, 13B) formed on a substrate, the optical splitter branching an input optical signal into N (N is an integer of 2 or more) optical signals, and outputting the optical signals, and N optical phase modulators (15A-15D) formed on the substrate for the respective optical signals output from the optical splitter, the optical phase modulators adjusting the phases of the optical signals based on a phase modulation characteristic in which the phase change amount changes depending on the wavelength of light, and output the optical signals.Type: ApplicationFiled: September 21, 2012Publication date: August 21, 2014Applicants: NTT ELECTRONICS CORPORATION, NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Atsushi Wakatsuki, Tadao Ishibashi
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Patent number: 8754445Abstract: A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.Type: GrantFiled: January 20, 2012Date of Patent: June 17, 2014Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone CorporationInventors: Tadao Ishibashi, Seigo Ando, Yoshifumi Muramoto, Toshihide Yoshimatsu, Haruki Yokoyama
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Patent number: 8729602Abstract: An APD is provided with a semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side of the first mesa, and in the APD, a total donor concentration of the n-type electric field control layer is lower than a total acceptor concentration of the p-type electric field control layeType: GrantFiled: September 1, 2011Date of Patent: May 20, 2014Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone CorporationInventors: Tadao Ishibashi, Seigo Ando, Masahiro Nada, Yoshifumi Muramoto, Haruki Yokoyama
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Publication number: 20130343697Abstract: An integrated optoelectronic module comprising: a semiconductor substrate; a single-mode optical waveguide comprising a semiconductor with a signal input section at a first end; a multi-mode optical waveguide comprising a semiconductor connected to a second end of the single-mode optical waveguide; and a photodiode disposed on and adjacent to the multi-mode interferometer waveguide and having at least one optical absorption layer section, wherein the single-mode optical waveguide, the multi-mode optical waveguide, and the photodiode being stacked on the semiconductor substrate, wherein the multi-mode interferometer waveguide comprises a reflection section formed by partly grooving the multi-mode interferometer waveguide, and an optical signal having propagated through the multi-mode interferometer waveguide is reflected by the reflection section and focused on the optical absorption layer section.Type: ApplicationFiled: June 17, 2013Publication date: December 26, 2013Inventor: Tadao Ishibashi
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Publication number: 20130313608Abstract: A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.Type: ApplicationFiled: January 20, 2012Publication date: November 28, 2013Applicants: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, NTT ELECTRONICS CORPORATIONInventors: Tadao Ishibashi, Seigo Ando, Yoshifumi Muramoto, Toshihide Yoshimatsu, Haruki Yokoyama
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Patent number: 8575650Abstract: An electron injected APD with an embedded n electrode structure in which edge breakdown can be suppressed without controlling the doping profile of an n-type region of the embedded n electrode structure with high precision. The APD comprising a buffer layer with a low ionization rate is inserted between an n electrode connecting layer and an avalanche multiplication layer. Specifically, the APD is an electron injected APD in which an n electrode layer, the n electrode connecting layer, the buffer layer, the avalanche multiplication layer, an electric field control layer, a band gap gradient layer, a low-concentration light absorbing layer, a p-type light absorbing layer, and a p electrode layer are sequentially stacked, and a light absorbing portion that includes at least the low-concentration light absorbing layer and the p-type light absorbing layer forms a mesa shape.Type: GrantFiled: December 11, 2009Date of Patent: November 5, 2013Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone CorporationInventors: Tadao Ishibashi, Seigo Ando, Yoshifumi Muramoto, Fumito Nakajima, Haruki Yokoyama
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Publication number: 20130168793Abstract: An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an outType: ApplicationFiled: September 1, 2011Publication date: July 4, 2013Applicant: NTT ELECTRONICS CORPORATIONInventors: Tadao Ishibashi, Seigo Ando, Masahiro Nada, Yoshifumi Muramoto, Haruki Yokoyama
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Publication number: 20130154045Abstract: An APD is provided with a semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side of the first mesa, and in the APD, a total donor concentration of the n-type electric field control layer is lower than a total acceptor concentration of the p-type electric field control layeType: ApplicationFiled: September 1, 2011Publication date: June 20, 2013Applicants: Nippon Telegraph and Telephone Corporation, NTT Electronics CorporationInventors: Tadao Ishibashi, Seigo Ando, Masahiro Nada, Yoshifumi Muramoto, Haruki Yokoyama
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Patent number: 8401344Abstract: A semiconductor optical modulator that includes a first semiconductor optical waveguide having a laminated structure including a core layer, a first clad layer, a second clad layer, and a barrier layer, the first clad layer and the second clad layer being disposed below and above the core layer, the barrier layer being inserted between the second clad layer and the core layer; a second semiconductor optical waveguide having a laminated structure in which the second clad layer has a p-type semiconductor penetrating locally through a n-type semiconductor in a laminated direction in the laminated structure of the first semiconductor optical waveguide; a first electrode connected to the first clad layer of the first semiconductor optical waveguide; and a second electrode electrically connecting the second clad layer of the first semiconductor optical waveguide and the p-type semiconductor of the second clad layer of the second semiconductor optical waveguide.Type: GrantFiled: December 26, 2008Date of Patent: March 19, 2013Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone CorporationInventors: Tadao Ishibashi, Kazuhiro Maruyama, Kenji Kobayashi, Tomoyuki Akeyoshi, Nobuhiro Kikuchi, Ken Tsuzuki, Mitsuteru Ishikawa
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Publication number: 20110241150Abstract: An electron injected APD with an embedded n electrode structure in which edge breakdown can be suppressed without controlling the doping profile of an n-type region of the embedded n electrode structure with high precision. The APD comprising a buffer layer with a low ionization rate is inserted between an n electrode connecting layer and an avalanche multiplication layer. Specifically, the APD is an electron injected APD in which an n electrode layer, the n electrode connecting layer, the buffer layer, the avalanche multiplication layer, an electric field control layer, a band gap gradient layer, a low-concentration light absorbing layer, a p-type light absorbing layer, and a p electrode layer are sequentially stacked, and a light absorbing portion that includes at least the low-concentration light absorbing layer and the p-type light absorbing layer forms a mesa shape.Type: ApplicationFiled: December 11, 2009Publication date: October 6, 2011Inventors: Tadao Ishibashi, Seigo Ando, Yoshifumi Muramoto, Fumito Nakajima, Haruki Yokoyama
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Patent number: 8031984Abstract: The present invention can provide an npin-type optical modulator that has a high withstand voltage and is easily fabricated. A semiconductor optical amplifier (10) according to an embodiment of the present invention is an npin-type semiconductor optical modulator in which layers are sequentially stacked, with a cathode layer (12-1) arranged on the substrate side, including at least a first n-type cladding layer (13-1), a p-type cladding layer (14), a core layer (17) and a second n-type cladding layer (13-2). In this semiconductor optical modulator, the p-type cladding layer (14) is electrically connected to an electrode (18-1) of the cathode layer. Accordingly, the accumulation of holes in the p-type cladding layer associated with light absorption in the npin-type optical modulator can be absorbed in the electrode on the negative side.Type: GrantFiled: October 24, 2007Date of Patent: October 4, 2011Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone CorporationInventors: Tadao Ishibashi, Nobuhiro Kikuchi, Ken Tsuzuki